Method and apparatus for eliminating double bit errosion in a di

Details Method and apparatus for eliminating double bit errosion in a di Method and apparatus for eliminating double bit errosion in a di

1980-08-07

1982-08-24

Atkinson, Charles E.

Excavating

371 43, G06F 1110

Patent

active

043464726

ABSTRACT:
A code converting circuit of simple construction composed of an exclusive OR circuit and a flip-flop circuit is provided on each of transmitting and receiving sides of a digital data transmission system according to a differential phase shift keying system, to convert two consecutive errors on adjacent bits peculiar to the differential phase shift keying system into only an error on a single bit. As a result, it is not required to employ a code having an excellent error-correcting capacity in the digital data transmission system, and thus a high transmission efficiency is attained by the use of a code which is relatively deficient in error correcting capacity.

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patent: 4035767 (1977-07-01), Chen et al.
patent: 4128828 (1978-12-01), Samejima et al.
patent: 4211996 (1980-07-01), Nakamura
Forney, Jr. and Bower, A High-Speed Sequential Decoder: Proto-type Design and Test, IEEE Trans. on Comm. Tech., vol. COM-19, No. 5, Oct. 1971, pp. 821-835.

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