Method and apparatus for eliminating branches using conditional

Details Method and apparatus for eliminating branches using conditional Method and apparatus for eliminating branches using conditional

1994-05-31

1995-11-21

Kulik, Paul V.

Boots, shoes, and leggings

395775, 395800, 364DIG1, 3642318, 36423223, 3642613, 3642619, 3642627, 364263, G06F 9315, G06F 938, G06F 1576

Patent

active

054695511

ABSTRACT:
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

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