Boots – shoes – and leggings
Patent
1998-01-29
2000-01-18
Teska, Kevin J.
Boots, shoes, and leggings
39550009, 364 51, 364 63, 364154, G11C 11407
Patent
active
060163909
ABSTRACT:
Disclosed is a method of designing a memory device that has substantially reduced bitline voltage offsets. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a six transistor core cell having a bitline and a complementary bitline, and designing a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a six transistor core cell followed by a flipped six transistor core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the six transistor core cell is coupled with the flipped complementary bitline of the flipped six transistor core cell, and the complementary bitline of the six transistor core cell is coupled to the flipped bitline of the flipped six transistor core cell.
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Becker Scott T.
Mali James C.
Artisan Components Inc.
Sergent Douglas W.
Teska Kevin J.
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