Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-12-12
2004-03-23
Tsai, H. Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S723000, C257S726000, C414S788000, C414S217000
Reexamination Certificate
active
06710436
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to techniques for assembling systems comprised of integrated circuits. More specifically, the present invention relates to a method and an apparatus that uses electrostatic forces to precisely align semiconductor chips relative to each other to facilitate system assembly.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, into a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
Unfortunately, these advances in semiconductor technology have not been matched by corresponding advances inter-chip communication technology. Semiconductor chips are typically integrated onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication. However, signal lines on a semiconductor chip are about 100 times more densely packed than signal lines on a printed circuit board. Consequently, only a tiny fraction of the signal lines on a semiconductor chip can be routed across the printed circuit board to other chips. This problem is beginning to create a bottleneck that continues to grow as semiconductor integration densities continue to increase.
Researchers have begun to investigate alternative techniques for communicating between semiconductor chips. One promising technique involves directly connecting two or more chips together face-to-face. In such an arrangement, hundreds or thousands of pads on the top-side of each chip come in contact or close proximity to matching pads on the other chip. Hence, the density of connections is very high and the distance the signals must travel is measured in microns instead of millimeters or centimeters.
In such a chip-to-chip scheme, there are several techniques by which electrical connections may be made between the pads. One technique is to provide solder balls on the pads of one chip. If the chips are placed face-to-face and nearly aligned, heating the solder balls makes electrical contact with the matching pads on the second chip and surface tension pulls the second chip into precise alignment.
Another technique is to communicate through capacitive coupling rather than through a direct connection. In this technique, each chip is manufactured with metal pads covered with an insulating layer of overglass about one micron thick. These chips are positioned face-to-face with the pads aligned. Capacitive coupling causes a voltage change on a transmitter pad to induce a voltage change on a corresponding receiver pad of the facing chip. This makes it possible to transmit signals directly between the chips without having to route the signal through intervening signal lines within a printed circuit board.
However, this technique requires precise alignment of chips without the benefit of surface tension pulling nearly aligned structures into precise alignment. Note that it is possible to align the facing chips precisely with micromanipulators, especially if electrical measurements of the quality of alignment can be made during the alignment process. However, use of such micromanipulators is time-consuming and expensive.
Hence, what is needed is a method and an apparatus for aligning semiconductor chips relative to each other without the problems listed above.
SUMMARY
One embodiment of the present invention provides a system that uses electrostatic forces to align semiconductor chips relative to each other. The system operates by fabricating a first set of conductors on the top surface of a first chip and fabricating a corresponding second set of conductors on the top surface of a second chip. To align the chips, the system electrically charges the first set of conductors and the second set of conductors. The system also places the first chip face-to-face with the second chip, so that the first set of conductors is in close proximity to the second set of conductors. This allows electrostatic forces between the first set of conductors and the second set of conductors to bring the first chip into alignment with the second chip and to hold them in place.
In a variation on this embodiment, the process of electrically charging the first set of conductors and the second set of conductors takes place after the first chip is placed face-to-face with the second chip.
In a variation on this embodiment, the process of electrically charging the first set of conductors and the second set of conductors involves applying a changing pattern of voltages to the first set of conductors and the second set of conductors.
In a variation on this embodiment, the system additionally vibrates the first chip and/or the second chip to facilitate aligning the first chip and the second chip.
In a variation on this embodiment, the system additionally applies a lubricant between the first chip and the second chip to reduce frictional forces between the first chip and the second chip during the alignment process.
In a variation on this embodiment, placing the first chip face-to-face with the second chip involves using a mold as a guide to facilitate bringing the first set of conductors in close proximity to the second set of conductors.
In a variation on this embodiment, a pattern formed by the first set of conductors matches a pattern formed by the second set of conductors.
In a variation on this embodiment, the first set of conductors and the second set of conductors are arranged in a checkerboard pattern.
In a variation on this embodiment, the first set of conductors and the second set of conductors are arranged in a pattern of concentric circles.
In a variation on this embodiment, the first set of conductors and the second set of conductors are arranged in a pattern with an autocorrelation approaching an impulse.
In a variation on this embodiment, the electrostatic forces between the first set of conductors and the second set of conductors include attractive forces and/or repulsive forces.
In a variation on this embodiment, the electrostatic forces between the first set of conductors and the second set of conductors generate a net repulsive force that levitates the first chip over the second chip, thereby reducing frictional forces between the first chip and the second chip.
In a variation on this embodiment, the first set of conductors comprises part of a power network and/or a ground network of the first chip.
In a variation on this embodiment, electrically charging the first set of conductors oil the first chip involves charging different conductors to different voltage levels.
In a variation on this embodiment, electrically charging the first set of conductors involves using electron-implanted charges.
In a variation on this embodiment, the system additionally bonds the first chip with the second chip after the first chip is brought into alignment with the second chip.
REFERENCES:
patent: 2003/0189201 (2003-10-01), Chen
Drost Robert J.
Harris David L.
Sutherland Ivan E.
Park Vaughan & Fleming LLP
Tsai H. Jey
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