Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1998-12-22
2002-09-17
Frejd, Russell (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C716S030000
Reexamination Certificate
active
06453276
ABSTRACT:
TECHNICAL FIELD
This invention relates to the field of logic simulation of electronic circuits. More specifically, this invention relates to methods and apparatus for efficiently generating test input for a logic simulator.
BACKGROUND OF THE INVENTION
Gordon Moore, the cofounder of Intel Corporation, made an observation and diction that semiconductor performance would double every 18 months, with the price of the new product remaining constant with the old. This observation is now referred to as Moore's Law, and has remained relatively accurate since the early 1970s. Moore's Law illustrates the rapid advancement that has and is taking place in the electronics industry. Because of this rapid advancement, the market window for many electronic products is relatively short, with faster and more powerful devices being continuously introduced. Accordingly, there is often great pressure to reduce the development time for many products. To significantly reduce the development time for most electronic devices, the design time must be reduced, as the design typically consumes a majority of the development cycle.
FIG. 1
shows a typical prior art design process for an ASIC (Application Specific Integrated Circuit) device. ASIC devices are commonly used to implement large and/or high performance circuit designs. In a first step, a hardware architect typically determines the requirements for the circuit design and formulates an underlying framework of the function and projected performance characteristics of the circuit design. The architect documents these ideas in a functional specification. This is shown at step
12
of FIG.
1
.
The design is then typically partitioned into a number of blocks and given to one or more logic designers for implementation. The logic designers create a detailed logic design using the functional specification as a guide. Rather than creating schematics, many logic designers express the design in a behavioral language such as VHDL (VHSIC Hardware Description Language), as shown at step
14
. Many logic simulation tools can directly accept behavioral language descriptions as input. This not only improves efficiency in developing complex circuit designs, but also allows various sections of the circuit design to be functionally verified before the entire design is complete.
As shown at step
16
, the design is typically logically simulated to verify the functionality thereof To logically simulate the design, the circuit designer typically provides one or more test input files. The test input files may include a number of test conditions often expressed as test vectors. Each of the test vectors may include a value for selected inputs of the circuit design along with an expected circuit response. The logic simulator reads the test input files, simulates the behavior of the circuit design using the test input, and provides a simulated circuit response. The simulated circuit response is then compared to the expected circuit response to determine if the circuit design provides the expected behavior.
To increase the speed of the logic simulator, a test driver may be provided. A test driver typically includes a memory structure or the like that is expressed in a behavioral language description, and is logically connected to the inputs of the circuit design. Prior to simulation, the memory structure of the test driver is loaded with data to control the inputs of the circuit design during logic simulation. For example, data may be loaded into a RAM structure within the test driver, and during logic simulation, the address to the RAM structure may be incremented to provide each of the test vectors to the inputs of the circuit design. The test driver, thus is simulated along with the circuit design. The use of a test driver may increase the speed of the logic simulation by allowing the simulation kernel of the logic simulation tool to run continuously for a longer period of time.
When a test driver is not used, the simulation kernel typically must be interrupted whenever new test vectors are applied. That is, without a test driver, each test vector must typically be applied via a simulation control program. Control must typically be passed between the simulation kernel and the simulation control program for each test vector to be applied. Because the simulation kernel must be continuously interrupted, the efficiency of the logic simulator is often reduced.
After logic simulation is complete, the design is typically passed to one or more physical designers, as shown at step
18
. The physical designers place the various cells that represent the basic logic building blocks of the circuit design, and interconnect the cells using a routing tool. Timing information may be extracted and analyzed by both the physical and logical designers. Some timing problems can be fixed by the physical designer by adjusting the drive strengths of various components or placing cells in a different arrangement relative to each other. As shown at step
22
, other timing problems can only be resolved by modifying the logic itself. If a problem is resolved by modifying the logic, the modified design must typically be reverified by re-executing logic simulation step
16
and then the physical design step
18
.
As shown at step
24
, after all the logical and physical changes are made, and the design meets the stated requirements, the design is released for fabrication. For a typical ASIC device, fabrication can take several months. Once completed, the device is returned and tested, as shown at step
26
. If the device does not meet the stated requirements, a design modification may be required as shown at step
22
, forcing another design iteration of the logic simulation step
16
, the physical design step
18
, and the fabrication step
24
. The device is again tested to determine if the design meets all of the stated requirements. If the device meets all of the stated requirements, the device is released, as shown at step
30
.
In most design processes, it is important to reduce the number of design iterations during the development cycle. Having more than one design iteration can substantially reduce the efficiency of the design process. One way of reducing the number of design iterations is to increase the fault coverage of the logic simulations. Increasing the fault coverage can increase the probability that the design errors will be detected before the design is fabricated. However, increasing the fault coverage increases the time required to generate and simulate the increased number of test cases. Thus, there is often a trade-off between the fault coverage and design cycle time.
FIG. 2
illustrates a prior art logic simulation process. At step
42
, the architect and test designer discuss the logic implementation and define a series of test cases that address the various functional sections and possible interactions of the design. In many designs, such as a MSU (Main Storage Unit) design with multiple parallel ports and crossbar switches (see below), there are many possible functional operations and interactions that should be tested. Thus, a large number of test cases are often required to achieve a high level of fault coverage.
For some of the test cases, the test designer can easily define the relevant test parameters. However, for many test cases, such as those that test parallel operating hardware, the test designer must use a certain level of parallel thinking and thus are much more difficult. A test case that simulates the interaction of two parallel operating ports of a circuit design, where the operation of one port must be choreographed with the operation of another port, is an example of a more complex test case. Defining such a test can require a significant amount of parallel thinking, and thus can be relatively difficult and time consuming.
Once the test cases are defined, the test designer typically codes the test cases into a format that can be used to produce an input for the logic simulator. The test designers may, for example, code the test cases into a format
Crompton Seager and Tufte, LLC
Frejd Russell
Johnson Charles A.
Starr Mark T.
Unisys Corporation
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