Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1998-12-21
2003-02-18
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S220000
Reexamination Certificate
active
06523106
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to a superscalar microprocessor and in particular to steering instructions down a pipe in such a microprocessor.
COPYRIGHT NOTICE/PERMISSION
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to the software and data as described below and in the drawings hereto: Copyright © 1997 Intel Corporation, All Rights Reserved.
BACKGROUND OF THE INVENTION
In a microprocessor with multiple pipelines, either each pipe must contain identical functional logic, since any instruction can be processed in any pipe, or particular instructions must be steered to a pipe which contains the specific functional logic necessary to process the instruction. Neither solution is wholly satisfactory.
Incorporating into each pipe the functional logic necessary to process all instructions in the instruction set for the microprocessor increases the total area of the microprocessor. As the density of logic in microprocessors increases, any additional area taken up by duplicating infrequently used functional logic across all the pipes introduces constraints on microprocessor design.
On the other hand, if only one pipe contains the particular functional logic, then steering logic must be incorporated into the microprocessor to ensure that the instruction which requires that logic is directed to the appropriate pipeline. Moreover, steering logic frequently introduces timing “bubbles” into the instruction stream, so complex timing logic is necessary to handle time-critical dependencies between instructions. Such steering and timing logic impacts the performance of the microprocessor and is difficult to design and debug.
Therefore, a need exists in the microprocessor art for a pipeline arrangement which minimizes the area required for the pipes while not requiring additional complex steering and timing logic.
SUMMARY OF THE INVENTION
Only one pipe in a superscalar microprocessor contains particular functional logic necessary to process a specific instruction. When the specific instruction appears in an instruction stream, the microprocessor replicates the specific instruction so that there are as many identical instructions in the instruction stream as there are pipes. The identical instructions appear contiguously in the instruction stream. Each identical instruction is processed by a different one of the pipes. The pipe with the particular functional logic performs the necessary operations for the specific instruction while the other pipes treat the instruction as if it were a null operation.
REFERENCES:
patent: 5555428 (1996-09-01), Radigan et al.
patent: 5966528 (1999-10-01), Wilkinson
patent: 6035391 (2000-03-01), Isaman
patent: 6047369 (2000-04-01), Colwell et al.
patent: 6094715 (2000-07-01), Wilkinson
interl, “iAPX 86/88, 186/188User's Manual”, 1985, pp. 3-1 to 3-18.
Morrison Mike
Mroczek Michael
Santoni Umberto
Zaidi Nazar A.
Niebling John F.
Whitmore Stacy A
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