Method and apparatus for efficient multi-stage FIR filters

Details Method and apparatus for efficient multi-stage FIR filters Method and apparatus for efficient multi-stage FIR filters

2005-04-13

2009-02-17

Ha, Dac V (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S230000, C708S303000, C708S319000, C708S322000, C341S061000

Reexamination Certificate

active

07492848

ABSTRACT:
An interpolation filter without a FIFO memory is configured as a cascade arrangement of simpler interpolation sub-filters that are operated in reverse order. The interpolation sub-filter that produces the highest sampling frequency is operated first, followed by interpolation sub-filters that operate at successively lower sampling frequencies. Computational independence of the cascaded sub-filters is guaranteed by adding delays to sampled and filtered signals. Delays are implemented by operating each of the cascaded sub-filters using prior filtering results that are computed during a previous sampling interval. A small increment to random-access memory is required for storing the successively delayed signals. The digital signal processor performing the filtering process is stalled for one clock cycle at the time a filtered signal sample is outputted so that the outputted signal sample can be produced without a timing conflict.

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