Method and apparatus for efficient matrix multiplication in...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C370S342000

Reexamination Certificate

active

10357124

ABSTRACT:
A system and method are disclosed for efficiently performing multiplication of an input vector and an input matrix having a limited number of possible values for any element of the input matrix. Elements of the input matrix are grouped across a second dimension of the input matrix to form groups of matrix elements. All possible permutations of partial results for each of the groups of matrix elements are pre-computed. The partial results from each of the groups of matrix elements are assigned to each of a corresponding index of a first dimension of the input matrix to form a matrix of assigned partial results. The assigned partial results are summed along the first dimension of the matrix of assigned partial results to form a vector of full matrix multiplication results.

REFERENCES:
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patent: 4914615 (1990-04-01), Karmarkar et al.
patent: 6895421 (2005-05-01), Dor et al.
Amira A et al: “Novel FPGA implementations of Walsh-Hadamard transforms for signal processing” IEE Proceedings: Vision, Image and Signal Processing, Institution of Electrical Engineers, GB, vol. 148, No. 6, Dec. 17, 2001, pp. 377-383.

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