Method and apparatus for efficient implementation of checksum ca

Details Method and apparatus for efficient implementation of checksum ca Method and apparatus for efficient implementation of checksum ca

1997-10-14

1999-06-15

Chung, Phung M.

Excavating

36474502, G06F 1110, H03M 1300

Patent

active

059129093

ABSTRACT:
An apparatus and method is disclosed for an improved implementation for calculating a checksum. The present invention includes a plurality of addition circuits forming at least a first and a final addition stage. The addition circuits receive a data bit stream and perform addition on data bit pairs emanating from the data bit stream to obtain a checksum value. Carry bits generated by the addition circuits are propagated as additional upper data bits until the final addition stage wherein the carry bits are added to lower bits to obtain a final checksum value. The data bit stream may be a sixty-four bit data stream such that the data bit pairs are four sixteen bit pairs. The final stage accepts a limited carry value input to guarantee that a final carry bit is not generated at the final addition stage. Thus, the checksum circuit propagates the carry bits from each addition down the pipeline wherein the carry bits can be added at the end rather than at each addition stage. Further, the checksum circuit guarantees that there will never be a carry-out at the final addition stage thus eliminating the need for a final adder or carry look-ahead logic.

REFERENCES:
patent: 5218563 (1993-06-01), Juri et al.
patent: 5329475 (1994-07-01), Juri et al.
J. Touch, B. Parham; Implementing the Internet Checksum in Hardware, ISI Informational Memo, Apr. 1996, pp. 1-21.

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