Method and apparatus for efficient cache refilling by the use of

Details Method and apparatus for efficient cache refilling by the use of Method and apparatus for efficient cache refilling by the use of

1994-06-24

1996-09-03

An, Meng-Ai T.

Boots, shoes, and leggings

395460, 3642434, 36424341, 36424345, 364DIG1, G06F 1212

Patent

active

055532640

ABSTRACT:
In the present invention, one of the bits in the tag value in the cache is hard-wired, for example, to 0, at such a position in the cache that that bit is always set to 0 when a tag is stored in the cache (or forced to 0 when a tag is read from the cache). Instructions executed by the processor can specify a read outside the cache, i.e. of the most recent data written to the main memory by some DMA agent, by specifying a read address with the designated bit equal to one. In this way, a cache miss is forced, allowing the processor to read the most recent data from the main memory of the system and to cache the data. As the cache is refilled from the main memory, the hard-wired tag bit of course remains set to zero. So later processor instructions that read data within the same cache refill block would use the normal address of that data (having the designated bit set to zero). These subsequent reads will not force a cache miss. Instructions executed by the processor can flush the cache by reading a sequence of addresses in which the designated tag bit is one. Since the designated bit is 0 in all cache tags, there will be misses on all words, so the entire cache will be filled from the main memory.

REFERENCES:
patent: 5001663 (1991-03-01), Parulski et al.
patent: 5155832 (1992-10-01), Hunt
patent: 5206941 (1993-04-01), Eikill et al.
patent: 5426765 (1995-06-01), Stevens et al.

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