Method and apparatus for early quotient completion in arithmetic

Details Method and apparatus for early quotient completion in arithmetic Method and apparatus for early quotient completion in arithmetic

1992-10-30

1994-07-12

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

053294769

ABSTRACT:
Apparatus and methods for early quotient completion in arithmetic division include a quotient digit generator, one or more asynchronous shift registers and a remainder comparison block. As quotient digits are generated, each digit is transferred to a different asynchronous shift register in turn. Digits are immediately propagated down each shift register to the next most significant digit position. During propagation digits are also repeated at all lesser significant digit positions. At the end of a digit generation cycle, when all asynchronous shift registers have received one new digit, the remainder comparison block determines if the current remainder is the same as the last period's remainder. If not, the remainder comparison block sends a reset signal to all the shift registers, sending reset spacers along each register that reset all duplicate versions of the last digits sent. The registers are then ready to receive next period's series of quotient digits. If the remainders are the same, the remainder comparison block halts any further quotient digit generation. Connections from each cell of the shift registers are interleaved to produce a final quotient answer that is already both correctly aligned, and has all repeating digits available and in place.

REFERENCES:
patent: 4011439 (1977-03-01), Bennett
patent: 4460970 (1984-07-01), McClary
"A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider" by Ted E. Williams and Mark A. Horowitz, IEEE Journal of Solid-State Circuits, vol. 26, No. 11, pp. 1651-1661, Nov. 1991.

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