Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2006-09-26
2010-06-29
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S228000, C712S225000, C712S216000
Reexamination Certificate
active
07747841
ABSTRACT:
A technique known as checkpointed early load retirement, combines register checkpointing load-value prediction to manage long-latency loads. When a long-latency load reaches the retirement stage unresolved, the processor enters Clear mode by (1) taking a Checkpoint of the architectural registers, (2) supplying a load-value prediction to consumers, and (3) early-retiring the long-latency load. This unclogs retirement, thereby “clearing the way” for subsequent instructions to retire, and also allowing instructions dependent on the long-latency load to execute sooner. When the actual value returns from memory, it is compared against the prediction. A misprediction causes the processor to roll back to the checkpoint, discarding all subsequent computation.
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Kirman Meyrem
Kirman Nevin
Martinez Jose F.
Alrobaye Idriss N
Chan Eddie P
Cornell Research Foundation Inc.
Jones Tullar & Cooper PC
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