Coded data generation or conversion – Digital code to digital code converters – To or from multi-level codes
Reexamination Certificate
2000-09-29
2001-11-13
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from multi-level codes
C358S461000, C355S019000
Reexamination Certificate
active
06317062
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to radio architectures, and more particularly to the generation multiple level decision thresholds of an M-ary coded signal.
BACKGROUND OF THE INVENTION
In high power digital architectures, the demodulated received signal is often found to be a good representation of the binary or M-ary code that was originally transmitted given that channel perturbations are small with regard to signal parameters. Such a demodulated signal, as shown in
FIG. 1
, represents an ideal signal which has relatively constant minimum and maximum peaks about a relatively constant threshold level. Such a signal may easily be converted into ones and zeroes through the use of hard limiters.
However in low power radio architectures that are presently required in wireless applications, the transmitted signals have low amplitudes and/or low FSK/PSK deviations for low bandwidths; therefore when detected are found to experience degradations from noise and such as Rayleigh/Ricean fading where the maximum and minimum peaks are far from constant. In addition, the frequency offsets between the transmitter and receiver, and the dc offsets in the circuitry will change the mean value of the demodulation level. In the case where a fixed threshold is used to determine the bit values, it may occur that some minimum peaks are above the threshold or some maximum peaks are below the threshold resulting in bit errors. One solution used in such cases is to generate a dynamic threshold which is calculated to be midway between a sequential maximum and minimum as illustrated in FIG.
2
. Though this type of solution has merit for the detection of binary signals, high bit error rates (BER) can still occur when detecting M-ary signals.
Therefore there is a need for quickly and dynamically generating decision thresholds that can effectively be used to decode signals having multiple levels.
SUMMARY OF THE INVENTION
The invention is directed to a method and apparatus for generating up to 2
m
−1 threshold levels where m ≧1 for decoding a demodulated M-ary level signal. It comprises detecting a maximum peak and a minimum peak in the M-ary level signal during each of sequential periods P, continuously averaging the maximum peaks and the minimum peaks over a number n of the sequential periods, and processing the coincident averages of the maximum peaks and the minimum peaks to provide the up to 2
m
−1 threshold levels.
In accordance with another aspect of the invention, during at least a programmed number of sequential periods P′, the 2
m
−1 threshold levels may initially be generated directly from the maximum peaks and the minimum peaks detected, and then be followed by 2
m
−1 threshold levels generated from the averages of the maximum peaks and the minimum peaks.
With regard to another aspect of this invention, the processor adds the averages of the maximum peaks with the coincident averages of the minimum peaks and divides the added averages by substantially two to provide a first decision threshold level. A second decision threshold level is produced by the processor by dividing the addition of the first threshold level and the averages of the maximum peaks by a factor &bgr;, while a third decision threshold level is produced by the processor by dividing the addition of the first threshold level and the averages of the minimum peaks by the factor &bgr;. The factor &bgr; may be in the order of 2.
In accordance with yet another aspect of this invention, an M-ary level signal may be decoded by comparing the M-ary level signal to the 2
m
−1 threshold levels. The M-ary level signal may also first be delayed before comparing to compensate for processing delays in generating the threshold levels.
With regard to a further aspect of this invention, the averaging circuits may comprise infinite impulse response filters. Each filter may comprise an input and an output terminal, a first amplifier having an input coupled to the input terminal and an output, a summing circuit having a first input, a second input and an output with the first input coupled to the first amplifier output and the output coupled to the output terminal, and a feedback circuit coupled between the summing circuit output and the summing circuit second input. The infinite impulse response filter may further comprise a second amplifier having an input coupled to the input terminal and an output, and a switch which has a first position for connecting the second amplifier output to the feedback circuit and a second position for connecting the summing circuit output to the feedback circuit.
Other aspects and advantages of the invention, as well as the structure and operation of various embodiments of the invention, will become apparent to those ordinarily skilled in the art upon review of the following description of the invention in conjunction with the accompanying drawings.
REFERENCES:
patent: 4624547 (1986-11-01), Endo et al.
patent: 4723173 (1988-02-01), Tanioka
patent: 5049990 (1991-09-01), Kondo et al.
patent: 5184316 (1993-02-01), Sugiyama
patent: 5210712 (1993-05-01), Saito
patent: 5732110 (1998-03-01), Richards
Watkins-Johnson Company Tech-Notes-vol. 7, No. 5, Sep./Oct. 1980, pp. 2-15 FSK: Signals and Demodulation-WATSON, Bob.
Birkett Neil
Payer Daniel
Nguyen John
Philsar Semiconductor Inc.
Thomas Kayden Horstemeyer & Risley LLP
Young Brian
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