Method and apparatus for dynamically expanding the pipeline of a

Details Method and apparatus for dynamically expanding the pipeline of a Method and apparatus for dynamically expanding the pipeline of a

1995-07-27

1996-12-31

Geckil, Mehmet B.

Boots, shoes, and leggings

395467, 364DIG1, 3642318, 3642405, G06F 938

Patent

active

055903681

ABSTRACT:
A dynamically expandable pipeline in a microprocessor. The present invention is used in a microprocessor or a microprocessor in a computer system. The present invention delays execution of a cacheable LOAD instruction by a bus controller for one cycle to allow sufficient time for "hit or miss" detection by a data cache unit. The present invention dynamically expands the instruction pipeline for cacheable LOAD instructions that "miss" an on-chip data cache when the LOAD is followed by another instruction that uses the bus controller. The dynamic pipeline allows time for the "hit or miss" detection by the data cache unit without unnecessarily degrading pipeline performance. The present invention offers increased overall microprocessor and computer system performance by allowing efficient implementation of an on-chip data cache. The present invention provides increased performance without undue or overly complex modifications to existing pipeline or data cache circuits.

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