Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1998-12-11
2002-06-04
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S458000, C370S413000
Reexamination Certificate
active
06400714
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of time slot interchangers for telecommunication transmission systems and, more particularly to an improved method and apparatus for dynamic time slot assignment.
2. Description of the Related Art
Digital loop carrier transmission systems, such as the Subscriber Loop Carrier (SLC®) transmission system by Lucent Technologies, rely on time slot interchangers (TSIs) to place digital information in appropriate time slots for transmission between customers and a local digital switch (known in the art as time slot assignment). Typically, these time slot interchangers have a resolution of 8-bits since most networks are based on 8-bit packets of information (an 8-bit packet will also be referred to herein as a “DS0 packet”).
The development of the Integrated Services Digital Network (ISDN) services allows voice, digital network services and video to be transmitted over a single wire or optical fiber in an effort to replace the current plain old telephone system (POTS) services. It is desirable to transmit the ISDN information on existing digital loop carrier systems. The ISDN information includes two channels, B
1
and B
2
, each containing 8-bit packets of information. The ISDN information, however, also includes a D-channel which consists of 2-bit packets of information. Therefore, the standard time slot interchanger and time slot assignment methods which are based on 8-bit packets must be altered to properly handle the 2-bit packets of the ISDN D-channel.
Previous methods have used an entire DS0 packet for the 2-bit D channel data. These methods waste precious bandwidth every time D channel information is being transmitted since the DS0 packet is ¾ empty. Other methods have rerouted DS0 packets containing solely D channel information multiple times through an 8-bit time slot interchanger. These methods use a 2-bit shifter to properly shift the 2-bits of information into a DS0 packet comprised of four sets of D channel data. These methods, however add a full frame of delay to the transmitted information.
Other methods oversample the information being input into the time slot interchanger. In these methods, the TSI is run at a rate that is four times the rate of the information being input into the TSI. Four time slots are subsequently combined to form one DS0. Since the oversampling is performed for all input information, even the 8-bit data, these methods cause the entire TSI to operate at ¼ its capacity and thus, would require other TSIs to avoid wasting bandwidth and to properly perform time slot assignment for 8-bit packet data. The additional TSIs add cost and processing overhead. Accordingly, there is a desire and need for a dynamic time slot assignment method and apparatus capable of handling 2-bit and 8-bit packets of information inexpensively, efficiently and using conventional time slot interchangers.
SUMMARY OF THE INVENTION
The present invention provides a dynamic time slot assignment method and apparatus capable of handling 2-bit and 8-bit packets of information inexpensively, efficiently and using conventional time slot interchangers.
The above and other features and advantages of the invention are achieved by providing a three stage method and apparatus for performing dynamic time slot assignment on both 2-bit and 8-bit information. In the first stage, 2-bit packets undergo a 2-bit time slot assignment prior to being sent to a conventional time slot interchanger. 8-bit information, however, is passed to the time slot interchanger without undergoing the 2-bit time slot assignment. The time slot interchanger performs time slot assignment on the 8-bit information to place the information in the appropriate outgoing DS0 time slots. In the second stage, the time slot interchanger places the 2-bit information into a fixed sequence of 8-bit time slots and passes these time slots to a packer. The prescribed time slots are established such that each time slot represents an assigned 2-bit location within a specific 8-bit time slot. The packer then combines the assigned time slots to create a serial stream of 8-bit time slots where each time slot contains up to four dynamically assigned 2-bit packets. In the third stage, the packed streams are routed back through the time slot interchanger for dynamic time slot assignment to place the information in the appropriate outgoing DS0 time slots. Accordingly, the method performs dynamic time slot assignment without additional time slot interchangers and unnecessary delays.
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Motyka Scott D.
Seiter Kenneth C.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Kizou Hassan
Lucent Technologies - Inc.
Spafford Tim
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