Multiplex communications – Diagnostic testing – Determination of communication parameters
Reexamination Certificate
1998-10-05
2001-11-13
Ngo, Ricky (Department: 2731)
Multiplex communications
Diagnostic testing
Determination of communication parameters
C370S462000, C370S502000, C710S107000, C327S262000
Reexamination Certificate
active
06317417
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the control of the signal characteristics of electronic signals and, more particularly, to the control of the characteristics of digital signal pulses transmitted on a parallel communication path.
BACKGROUND OF THE INVENTION
A common type of parallel bus is one that transmits signals in accordance with the Small Computer Standard Interface (SCSI) protocol. Such a bus has many conductors, including a plurality of parallel data lines and a clock line. Due to switching transients in the bus drivers and other circuitry, data signals on the plurality of data wires are stable during certain time intervals and unstable during other time intervals. It is important that devices connected to the bus read the data lines only during the time intervals during which the data signals are stable. Consequently, a signal on the clock wire is used to control the time period during which devices connected to the bus read data from the data lines.
The conventional SCSI bus arrangement works well, but limits the physical length of a SCSI bus. The data and clock signals propagate down the bus lines at slightly different speeds due to a variety of factors, and, as the bus gets longer, the differences in propagation speeds cause the data signals to arrive at a given point at different times, a phenomenon called “skew.” If the skew becomes large enough, it may shift the arrival of a data signal relative to the clock signal at a peripheral device by an amount sufficient to cause the data signal to be read in its unstable region, thereby causing a data error.
One prior art solution to this problem is to use a “store and forward” buffer system. In this arrangement, signals on the bus are received and stored until signals are received for each bus line. When all signals have been received, the signals are simultaneously retransmitted on another SCSI bus, thereby overcoming the skew problem. However, SCSI busses have a number of timing requirements that restrict the use of the buffering approach. For example, in accordance with conventional operation, a host computer transmits a signal to a peripheral device which then sends a signal back to the host. The host waits a predetermined amount of time to receive the response from the device. If a response is not received from the device in the predetermined amount of time, the message is considered as not received. This operation prevents any open-ended communications between a host and a peripheral device.
A certain amount of time is required for a signal to propagate from a host computer to the peripheral device. Accordingly, if an extremely long cable is used, the propagation time may be longer than the predetermined time that the host is going to wait. The prior art method of storing signals in a buffer exacerbates this problem and, if buffering is used, the SCSI bus cables must be physically shortened to accommodate the time lost while the information is stored in a buffer. In addition to the skew problem, the prior art buffering method is not effective for high-speed lines since it slows down transmission between two SCSI busses.
Another prior art method for overcoming the skewing problem is to introduce a delay circuit into each bus line at a remote position along the SCSI bus after the clock and data signals have traveled through the bus. Digital delay circuits are known in the art, and are used to generate an output signal that is a replica of an input signal, but which has pulse widths (i.e. the duration of its digital pulses) which are longer than that of the input signal. The delay circuits realign the bus signals to eliminate skew. One type of delay circuit utilized for this purpose is constructed from discrete circuit elements. This type of delay circuit does not provide consistent delay times because the delay times through the discrete elements can vary significantly with fluctuating operating conditions, such as temperature and voltage. Different variables in the manufacturing processes used to manufacture the discrete elements can also create variances from unit to unit. To overcome the latter problems, some circuits are manufactured by laser trimming some of the components after the circuit is assembled on a circuit-by-circuit basis in order to provide more accurate propagation delays. This is not economically desirable, however, because of the extra cost associated with the laser trimming process.
Other prior art devices use tunable delay circuits. These latter circuits monitor the actual delay times and adjust themselves to provide more consistent, non-varying delay times. For example, U.S. Pat. No. 5,087,842 (Pulsipher et al.), discloses a self-adjusting delay circuit that includes a set of voltage controlled delay elements in each bus line. A ring oscillator is constructed with the same voltage controlled delay element used in the bus lines. The output of the ring oscillator which is indicative of the actual delay time through each of the delay elements is provided to an external microprocessor that adjusts all of the delay elements including that in the ring oscillator until the delay as measured by the ring oscillator meets a predetermined value.
One other device is described in U.S. patent application Ser. No. 08/881,436, and makes use of a delay device that produces a substantially constant delay time. A delay circuit with a tapped delay element line and a multiplexer are used to select the signal at one of the taps to produce a variable delay through the circuit. A counter is used to count pulses produced by the oscillator, and a computation circuit for calculating the appropriate tap to select with the multiplexer.
SUMMARY OF THE INVENTION
The present invention provides an “expander” for a data transmission path that does adaptive pulse characteristic modification for the data transmitted along the data path. The expander reconditions each data pulse to compensate for pulse degradation, and optimize the pulse for a transmission rate used during the time that the pulse is transmitted. The invention includes a pulse receiving element and a pulse transmitting element that retransmits the received pulse with the desired modification, or modifications, to the pulse. This modification is relative to the transmission rate, and changes the pulse such that its transmission performance is improved at the determined transmission rate. in the preferred embodiment, the modified characteristic may be either or both of the pulse width and a propagation delay of the pulse relative to a second pulse.
The transmission path is accessible to a plurality of devices, each of which is capable of transmitting signal pulses over it, and receiving signal pulses from it. The transmission rate may be different for different combinations of transmitting and receiving devices. In the preferred embodiment, the transmission path is a SCSI bus, and each of the devices has an assigned identification (ID) value. Prior to a transmission, the transmission rate is negotiated between the two devices involved in the transmission. The invention monitors these negotiations, and determines the selected rate. A memory storage device is used to store an indication of the transmission rate for each combination of transmitting and receiving devices. After these values are stored for each combination of transmitting and receiving device, monitoring the negotiations for transmission rate is no longer necessary, since the value should always be the same for a given combination of devices, and has already been stored relative to that combination. Preferably, the device IDs themselves are used as an address to the appropriate storage location for a given rate.
In the preferred embodiment, the transmitting and receiving elements are the components of a delay line, which is capable of delaying the rising or the falling edge of a given pulse based on the delay line tap values provided to it. Indeed, several delay lines are preferably used, to provide desired pulse modifications to both pulse width and propagation delay, and to d
Childs Keith
Lee Fee
Compaq Computer Corporation
Conrad Philip L.
Hogan & Hartson LLP
Kubida William J.
Ngo Ricky
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