Patent
1993-08-25
1997-08-05
Ellis, Richard L.
G06F 938
Patent
active
056550960
ABSTRACT:
A computer processor employing parallelism through pipelining and/or multiple functional units improved by Sequential Coherency Instruction Scheduling and/or Sequential Coherency Exception Handling. Sequential Coherency Instruction Scheduling establishes dependencies based on the sequential order of instructions, to execute those instructions in an order that may differ from that sequential order. Instructions are permitted to execute when all needed source operands will be available by the time required by the instruction and when all logically previous reads and writes of the destination will be accomplished before the time that the instruction will overwrite the destination. Sequential Coherency Exception Handling does not use checkpointing or in-order commit. Instead it permits out-of-order execution to actually update the permanent state of the machine out-of-order. It maintains and saves, when an exception is recognized, sequential flow information and completion information about the program execution. To resume the exception causing program after the exception is handled, the saved state is used to re-establish the program flow that was determined prior to the exception and to re-establish which instructions in that flow should not be executed, because they were completed before the exception occurred.
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