Method and apparatus for dynamic power adjustment in a...

Details Method and apparatus for dynamic power adjustment in a... Method and apparatus for dynamic power adjustment in a...

2006-12-08

2009-06-16

Phung, Anh (Department: 2824)

Static information storage and retrieval

Powering

Conservation of power

C365S233100, C365S233140, C713S322000, C713S320000

Reexamination Certificate

active

07548481

ABSTRACT:
An aspect of the invention relates to a method of dynamically adjusting power consumption of a random access memory (RAM) coupled to a processor. Frequency of a memory clock signal coupled to the RAM is reduced. At least one supply voltage coupled to the RAM is reduced. At least one latency parameter of the RAM is configured in response to the reduced frequency and the reduced at least one supply voltage. The RAM may then be re-initialized. In this manner, voltage supplied to the RAM is reduced, thereby reducing power consumption in the RAM.

REFERENCES:
patent: 6845053 (2005-01-01), Chevallier
patent: 7237128 (2007-06-01), Naveh et al.
“SpeedStep”, Wikipedia, http://en.wikipedia.org/wiki/SpeedStep, Jun. 12, 2007, pp. 1-3.

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