Patent
1997-01-08
1999-06-29
Ellis, Richard L.
G06F 938
Patent
active
059180331
ABSTRACT:
A processor for executing a set of instructions, where each instruction in said set of instructions includes a set of operand references. The processor includes an instruction decoder for extracting the set of operand references from each instruction in the set of instructions; a register file decoder connected to the instruction decoder for receiving the set of operand references and generating a set of register data select signals; and, a register file connected to the register file decoder for receiving the set of register data select signals. Further, the register file includes: a set of registers; a first set of scoreboard bits; and, a second set of scoreboard bits; wherein for each signal in the set of register data select signals, the register file outputs: (1) a corresponding register from the set of registers; (2) a first corresponding scoreboard bit from the first set of scoreboard bits; and, (3) a second corresponding scoreboard bit from the second set of scoreboard bits.
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patent: 5546554 (1996-08-01), Yung et al.
Hinton, Glenn, 80960--Next Generation, IEEE, 1989, pp. 13-17.
Yoshida et al., A Strategy for Avoiding Pipeline Interlock Delays in a Microprocessor, LSI Research and Development Labroatory, IEEE 1990, pp. 14-19.
Heeb Jay
Schaecher Mark
Ellis Richard L.
Intel Corporation
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