Patent
1996-08-27
1998-02-24
Lall, Parshotam S.
395706, 395391, 395392, G06F 945
Patent
active
057218544
ABSTRACT:
An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is performed by an instruction stream interpreter unit (ISU), which is placed between the instruction cache and main memory. The conversion process is performed when an instruction cache miss occurs. Each line in the instruction cache contains a single compound instruction. The format of this compound instruction is transparent to programmers and will vary depending on the number of execution units which are to be supported.
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Ebcioglu Mahmut Kemal
Groves Randall Dean
Bailey Wayne P.
Henkler Richard A.
International Business Machines - Corporation
Lall Parshotam S.
McBurney Mark E.
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