Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1996-09-25
2002-02-26
Ho, Tuan (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S314000, C348S250000
Reexamination Certificate
active
06351284
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for driving a solid state image sensor, and, more particularly to a method and apparatus for transfering charge pakets in a solid state image sensor having a semiconductor substrate and a plurality of channel regions provided on the semiconductor substrate.
2. Description of the Related Art
An image sensing apparatus, which has a solid state image sensor like a CCD (Charge Coupled Device), controls the exposure of the solid state image sensor to acquire the optimal exposure state. This exposure control uses a iris mechanism which mechanically controls the amount of incident light to the solid state image sensor in accordance with the luminance of light reflected from a target object to be sensed. Alternatively, the exposure control can use a so-called electronic shutter which controls the period the solid state image sensor accumlates charges in accordance with the luminance of light reflected from a target object.
The solid state image sensor has light-receiving pixels (elements) arranged in a matrix form, which stores (accumlates) information charges that are generated in accordance with the incident light. When an overflow of information charges occurs at some of the light-receiving pixels, excess charges leak from such light-receiving pixels and the leaking charges tend to bloom with information charges stored in the light-receiving pixels that are adjacent or peripherally located thereto. To prevent such blooming, an overflow drain is provided adjacent to each light-receiving pixel.
FIG. 1
is a cross-sectional view of a light-receiving section
10
of a CCD solid state image sensor which employs a vertical overflow drain structure to absorb excess information charges on the substrate side. A diffusion region (P-well region)
12
having a P type conductivity is formed on the surface region of a semiconductor substrate
11
which has an N type conductivity and where a drain region is to be formed. Formed on the surface of this P-well region
12
is a diffusion layer (buried layer)
13
which has an N type conductivity and where a channel region
17
is to be formed. This buried layer
13
is so formed as to be defined by an isolation region (not shown) on the surface of the P-well region
12
and to extend in one direction. First gate electrodes
15
are arranged at given intervals on the buried layer
13
via an insulating layer
14
, and second gate electrodes
16
are arranged between the adjoining first gate electrodes
15
in such a way as to partially cover the individual gate electrodes
15
.
As shown in
FIG. 2
, the first and second gate electrodes
15
and
16
are respectively supplied with four-phase vertical clocks &phgr;v, each of which has a phase difference of 90 degrees from one to another and are synchronous with a vertical sync signal VD, and the semiconductor substrate
11
is supplied with a substrate clock &phgr;b. A ground voltage is applied to the P-well region
12
. In response to the vertical clock &phgr;v, the light-receiving section
10
quickly transfers the information charges in the unit of packet to a storage section (not shown) included in the CCD solid state image sensor during the blanking period for vertical scanning. In response to the substrate clock &phgr;b, the light-receiving section
10
discharges the stored information charges. Therefore, the information-charge storing period of the light-receiving section
10
is indicated by a period L from the point of completion of the discharging of the information charge packets by the substrate clock &phgr;b to the beginning of the transfer of the information charge packets by the vertical clock &phgr;v. Alteration of the supply timing for this substrate clock &phgr;b permits the information-charge storing period or the shutter speed to be controlled.
In the vertical overflow drain structure, at the time the light-receiving section
10
stores information charges, the substrate clock &phgr;b is held at the low level, and one, two or three of the four-phase vertical clocks &phgr;v are kept at the high level and the remaining of clocks is kept at low level. As a result, the first and second gate electrodes
15
and
16
are selectively enabled. In a part of the light-receiving section
10
where the first and second gate electrodes
15
and
16
are enabled, as shown in
FIG. 2
, a potential well (depletion layer) is formed in the channel region
17
in the buried layer
13
and a potential barrier is formed in the P-well region
12
. Accordingly, information charges are stored in the space from within the buried layer
13
to the surface of the P-well region
12
. In another part of the light-receiving section
10
where the first and second gate electrodes
15
and
16
are disabled, a potential well is not formed in the buried layer
13
but a potential barrier for defining the light-receiving pixels is formed therein.
In the shutter operation for simultaneously discharging information charges stored in the individual light-receiving pixels, all the vertical clocks &phgr;v are kept at the low level and the substrate clock &phgr;b rises. Consequently, the potential well in the buried layer
13
becomes shallower while the potential well in the semiconductor substrate
11
becomes deeper. As a result, the potential barrier in the P-well region
12
disappears as indicated by the broken line in FIG.
3
. In this manner, the information charges stored in the potential well in the buried layer
13
are moved to the semiconductor substrate
11
from the buried layer
13
along the potential profile and are discharged therefrom.
At the time of sensing an image, information charges are stored in the same channel regions
17
in the buried layer
13
. At the time of reading the information charges, the information charge packets are transferred from those channel regions
17
. At this time, the charge storing performance at the image sensing time differs from the charge transfer performance at the reading time. More specifically, at the image sensing time, a given voltage is applied to the first and second gate electrodes
15
and
16
to thereby fix the potential in the buried layer
13
. The information charges are therefore stored in the channel regions
17
in the buried layer
13
without being affected by a delay in the potential variation.
At the reading time, however, a clock having a high frequency is supplied to the first and second gate electrodes
15
and
16
so that the potential alternatively varies. Even if the delay in the potential variation is generated and the same voltage as the one applied at the image sensing time is applied to the gates, the same amount of information charges as that produced at the image sensing time cannot be accumulated in the channel regions
17
. In other words, the charge transfer performance at the reading time becomes smaller than the charge storing performance at the image sensing time. If the maximum amount of information charges allowed by the performance are stored in the channel regions
17
at the image sensing time, therefore, some of the charges will remain untransferred in the channel regions
17
after the reading time. For example, when bright spot light from a part of a target object is incident, some of the charges will remain untransferred in the channel regions
17
. The remaining charges are added to those information charges which are stored in the subsequent light-receiving pixels at the time charge packets are transferred along the buried layer
13
. This undesirable effect results in the deterioration of the quality of reproduced images.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention relates to a method and apparatus for driving a solid state image sensor such that the amount of information charges remaining in the channel regions at the time of transferring the information charges stored in the channel regions is significantly reduced.
The invention can be implemented in numerous ways, including as a m
Nakano Shuichi
Watanabe Tohru
Ho Tuan
Sanyo Electric Co,. Ltd.
Sheridan & Ross P.C.
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