Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2001-01-12
2002-06-18
Wong, Don (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C345S060000, C345S076000, C345S078000
Reexamination Certificate
active
06407510
ABSTRACT:
BACKGROUND OF TH INVENTION
1. Field of the Invention
This invention relates to a technique for driving a plasma display panel, and more particularly to a plasma display panel driving method that permits a high-speed addressing. The present invention also is directed to a plasma display panel driving apparatus.
2. Description of the Related Art
Recently, a plasma display panel (PDP) feasible to a manufacturing of a large-dimension panel has been highlighted as a flat panel display device. The PDP typically includes a three-electrode, alternating current (AC) surface discharge PDP that has three electrodes and is driven with an AC voltage as shown in FIG.
1
.
Referring to
FIG. 1
, a discharge cell of the three-electrode, AC surface discharge PDP includes a scanning/sustaining electrode
12
Y and a common sustaining electrode
12
Z formed on an upper substrate
10
, and an address electrode
20
X formed on a lower substrate
18
. On the upper substrate
10
in which the scanning/sustaining electrode
12
Y is formed in parallel to the common sustaining electrode
12
Z, an upper dielectric layer
14
and a protective film
16
are disposed. Wall charges generated upon plasma discharge are accumulated in the upper dielectric layer
14
. The protective film
16
prevents a damage of the upper dielectric layer
14
caused by the sputtering generated during the plasma discharge and improves the emission efficiency of secondary electrons. This protective film
16
is usually made from MgO. A lower dielectric layer
22
and barrier ribs
24
are formed on the lower substrate
18
provided with the address electrode
20
X, and a fluorescent material
26
is coated on the surfaces of the lower dielectric layer
22
and the barrier ribs
24
. The address electrode
20
X is formed in a direction crossing the scanning/sustaining electrode
12
Y and the common sustaining electrode
12
Z. The barrier ribs
24
is formed in parallel to the address electrode
20
X to prevent an ultraviolet ray and a visible light generated by the discharge from being leaked to the adjacent discharge cells. The fluorescent material
26
is excited by an ultraviolet ray generated upon plasma discharge to produce a red, green or blue color visible light ray. An active gas for a gas discharge is injected into a discharge space defined between the upper/lower substrate and the barrier rib.
As shown in
FIG. 2
, such a discharge cell is arranged in a matrix type. In
FIG. 2
, the discharge cell
1
is provided at each intersection among scanning/sustaining electrode lines Y
1
to Ym, common sustaining electrode lines Z
1
to Zm and address electrode lines X
1
to Xn. The scanning/sustaining electrode lines Y
1
to Ym are sequentially driven while the common sustaining electrode lines Z
1
to Zm are commonly driven. The address electrode lines X
1
to Xn are driven with being divided into odd-numbered lines and even-numbered lines.
Such a three-electrode, AC surface discharge PDP is driven with being separated into a number of sub-fields. In each sub-field interval, a light emission having a frequency proportional to a weighting value of a video data is conducted to provide a gray scale display. For instance, if a 8-bit video data is used to display a picture of 256 gray scales, then one frame display interval (e.g., {fraction (1/60)}second=16.7 msec) in each discharge cell
1
is divided into 8 sub-fields SF
1
to SF
8
as shown in FIG.
3
. Each sub-field SF
1
to SF
8
is again divided into a reset interval, an address interval and a sustaining interval. A weighting value at a ratio of 1:2:4:8: . . . :128 is given in the sustaining interval. Herein, the reset interval is a period for initializing the discharge cell; the address interval is a period for generating a selective address discharge in accordance with a logical value of a video data; and the sustaining interval is a period for sustaining the discharge in a discharge cell in which the address discharge has been generated. The reset interval and the address interval are equally assigned in each sub-field interval.
FIG. 4
is waveform diagrams according to a conventional PDP driving method. Referring to
FIG. 4
, all of the cells are initialized by a reset discharge generated in the reset interval (not shown). In the address interval, a scanning pulse SP is sequentially applied to the scanning/sustaining electrode lines Y
1
to Ym and a data pulse DP synchronized with the scanning pulse SP is applied to the address electrode lines X
1
to Xn. At this time, an address discharge is generated at discharge cells supplied with the data pulse DP. In the sustaining interval, sustaining pulses SUSPy and SUSPz are alternately applied to the scanning/sustaining electrode lines Y
1
to Ym and the common sustaining electrode lines Z
1
to Zm to cause a sustaining discharge at the discharge cells selected by the address discharge.
In such a sub-field driving method, the sustaining interval must assure a sufficient time for a picture display interval so as to show an appropriate brightness. However, as a-PDP has a higher resolution, that is, as the number of scanning/sustaining electrode lines Y is more increased, an address interval for selecting the discharge cells are more enlarged. If an address interval is enlarged as mentioned above, then the sustaining interval for displaying a picture becomes relatively short to deteriorate a brightness of the PDP.
In order to solve the above-mentioned problem, a scheme of reducing a pulse width for the address discharge has been used. If a pulse width for the address discharge is reduced, however, the address discharge becomes unstable to increase an address failure probability. Particularly, if the number of the scanning/sustaining electrode lines Y is increased, then an address discharge should be generated for a very short time of about 1 &mgr;s per line. However, an address discharge at 1 &mgr;s fails to form sufficient wall charges at the discharge cells. A state of spatial charges become different for each discharge cell and an address discharge become unstable due to an affect of adjacent cells. As a result, a scheme capable of shortening an address interval in a state of keeping an address discharge time at more than 1 &mgr;s is required.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a plasma display panel (PDP) driving method and apparatus that permit a high-speed addressing.
In order to achieve these and other objects of the invention, a method of driving a plasma display panel according to one aspect of the present invention includes the steps of applying a data pulse to address electrodes in an address interval for selecting discharge cells; applying an auxiliary data pulse to the address electrodes in such a manner to be positioned at the front and rear portions of the data pulse when the data pulse is applied to the address electrodes; and sequentially applying a scanning pulse to scanning/sustaining electrodes.
A method of driving a plasma display panel according to another aspect of the present invention includes the steps of sequentially applying a scanning pulse to scanning/sustaining electrodes in an address interval for selecting discharge cells; applying an auxiliary scanning pulse in such a manner to be positioned at the front portion of the scanning pulse and overlap with the previous scanning pulse when the scanning pulse is applied to the scanning/sustaining electrodes; and applying any one of first and second data pulses having a different pulse width depending on a logical value of a data to address electrodes in an address interval.
A driving apparatus for a plasma display panel according to still another aspect of the present invention includes a plurality of shift registers to each of which a data is inputted; a plurality of memories for receiving said data stored in the shift registers and temporarily storing the received data; an auxiliary data generator for receiving said data stored in the memories to generate an auxiliary data; and an output de
Myoung Dae Jin
Song Byung Soo
Yoo Jun Yeong
Fleshner & Kim LLP
LG Electronics Inc.
Vo Tuyet T.
Wong Don
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