Method and apparatus for doubling a clock signal using phase int

Details Method and apparatus for doubling a clock signal using phase int Method and apparatus for doubling a clock signal using phase int

1997-03-31

1999-01-26

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327116, H03B 1900

Patent

active

058642463

ABSTRACT:
A circuit for multiplying a clock signal. The circuit includes a phase interpolator having two inputs for receiving complementary clock signals. The output of the phase interpolator is connected to an input in an exclusive OR gate. One of the two complementary input signals also is sent into the exclusive OR gate, wherein a multiplied clock signal is generated at the output of the exclusive OR gate.

REFERENCES:
patent: 3778727 (1973-12-01), Williams
patent: 3911368 (1975-10-01), Tarczy-Hornoch
patent: 4267514 (1981-05-01), Kimsey
patent: 4737721 (1988-04-01), Lippl
patent: 4851785 (1989-07-01), Gehrt et al.
patent: 4949364 (1990-08-01), Yukawa
patent: 4956797 (1990-09-01), Berard
patent: 5297179 (1994-03-01), Tatsumi
patent: 5399995 (1995-03-01), Kardontchik et al.
patent: 5448196 (1995-09-01), Kanbara et al.
patent: 5485490 (1996-01-01), Leung et al.
patent: 5554945 (1996-09-01), Lee et al.
patent: 5614841 (1997-03-01), Marbot et al.
Serial IO Interpolator Discussion "Phase Interpolator"; http://iram.cs.berkeley.edu/serialio/cs254/interpolator/interp.html.
Sidiropoulos, S. and Horowitz, M., "A Semidigital Dual Delay-Locked Loop"; IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997.
Horowitz, M. et al.; ISSCC 1993 IEEE International Solid-State Circuits Conference; Session 10, High-Speed Communication and Interfaces; Paper TP 10.5, "PLL Design for a 500 MB/s Interface".

Affiliated with

Also associated with

Rating

Method and apparatus for doubling a clock signal using phase int does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for doubling a clock signal using phase int, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for doubling a clock signal using phase int will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1452982