Method and apparatus for doping a melt with a dopant

Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth from liquid or supercritical state – Having pulling during growth

Reexamination Certificate

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C117S200000, C117S208000, C117S214000

Reexamination Certificate

active

06660082

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for doping a melt with a dopant, the melt being provided in a crucible. The invention also relates to an apparatus which is suitable for carrying out the method.
2. The Prior Art
The invention is advantageous for the production of single crystals from semiconductor material, which are pulled out of a melt using the Czochralski method and serve as base material for the fabrication of electronic components. The melt generally consists of molten silicon to which a dopant is added. When the dopant is being introduced into the melt, there may be problems with splashing of molten material or the dopant may be difficult to control on account of its volatility. Highly volatile dopants, such as antimony or arsenic, unlike, for example, boron or phosphorus, cannot be melted in the crucible together with polycrystalline semiconductor material. This is because they would evaporate out during the melting process. Therefore, these dopants are usually added only just before the single crystal is pulled from the melt.
Furthermore, the volatility of some dopants causes a series of problems during the pulling operation. Uncontrollable evaporation of the dopant leads to deviations in the resistance and therefore to single crystals which cannot be used. Highly inflammable and generally toxic coatings and particles are deposited in the drawing installation and in the filter system, requiring a considerable outlay on cleaning. If, during the pulling operation, particles fall into the melt, defects may be formed in the crystal, making the single crystal produced unusable. Therefore, it is necessary to use a doping method which involves minimal evaporation losses.
There are already various publications, such as WO-97/36024, JP-62-153188, JP-60-171291 and U.S. Pat. No. 5,406,905, which relate to the doping of a melt. However, none of these publications provides a comprehensive solution to the problems outlined above.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a solution to problems of this type.
The above object is achieved according to the present invention by providing a method for doping a melt with a dopant, the melt being provided in a crucible, wherein the dopant is introduced into a vessel and the vessel is immersed in the melt, the dopant being transferred into the melt through an opening which forms in the vessel.
The present invention also relates to an apparatus for doping a melt with a dopant, which has a vessel containing the dopant and a device which is connected to the vessel, for lowering the vessel into a melt in a crucible and for lifting the vessel out of the melt, the vessel being provided with an opening which is blocked by a closure piece which is of the same type of material as the melt and melts when it is brought into contact with the melt.
The method can be carried out using all customary dopants. However, it is particularly suitable for doping a melt of semiconductor material, such as silicon, with highly volatile dopants, such as arsenic or antimony. The method and three preferred embodiments of the apparatus are described in more detail below with reference to drawings.


REFERENCES:
patent: 4973454 (1990-11-01), Morioka et al.
patent: 5360480 (1994-11-01), Altekruger
patent: 5406905 (1995-04-01), Yemane-Berhane et al.
patent: 5427056 (1995-06-01), Imai et al.
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patent: 5580171 (1996-12-01), Lim et al.
patent: 5587016 (1996-12-01), Altekruger et al.
patent: 5720810 (1998-02-01), Arai et al.
patent: 5876496 (1999-03-01), Nagai et al.
patent: 5900055 (1999-05-01), Nagai et al.
patent: 5976245 (1999-11-01), Aydelott
patent: 6179914 (2001-01-01), Aydelott
patent: 60-171291 (1985-09-01), None
patent: 62-153188 (1987-07-01), None
patent: 97/36024 (1997-10-01), None
Wolf et al., Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, USA, pp. 30-33, 1986.*
English Derwent Abstract AN 1987-230720 [33] corresponding to JP 62-153188.
English Derwent Abstract AN 1985-258959 [42] corresponding to JP 60-171291.

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