Method and apparatus for dithering in multi-bit sigma-delta...

Details Method and apparatus for dithering in multi-bit sigma-delta... Method and apparatus for dithering in multi-bit sigma-delta...

2011-06-14

2011-06-14

Nguyen, Khai M (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Increasing converter resolution

C341S143000, C341S155000

Reexamination Certificate

active

07961126

ABSTRACT:
A multi-bit (M-bit, M>1) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log 2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

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