Method and apparatus for dithering in multi-bit sigma-delta...

Details Method and apparatus for dithering in multi-bit sigma-delta... Method and apparatus for dithering in multi-bit sigma-delta...

2011-06-14

2011-06-14

Nguyen, Khai M (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Increasing converter resolution

C341S143000, C341S144000

Reexamination Certificate

active

07961125

ABSTRACT:
A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M−N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

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