Data processing: generic control systems or specific application – Generic control system – apparatus or process – Plural processors
Patent
1997-10-24
2000-08-08
Gordon, Paul P.
Data processing: generic control systems or specific application
Generic control system, apparatus or process
Plural processors
200 2, 200 3, 200 19, 200 20, 709201, 709215, 709216, 712 28, 712 29, 712 32, G05B 1918
Patent
active
061014206
ABSTRACT:
An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
REFERENCES:
patent: 5297269 (1994-03-01), Donaldson et al.
patent: 5317720 (1994-05-01), Stamm et al.
patent: 5481689 (1996-01-01), Stamm et al.
patent: 5542058 (1996-07-01), Brown, III et al.
patent: 5566310 (1996-10-01), Mathewson, II
patent: 5634015 (1997-05-01), Chang et al.
patent: 5740348 (1998-04-01), Cunliffe et al.
patent: 5809320 (1998-09-01), Jain et al.
Gharachorloo Kourosh
Sharma Madhumitra
Steely Simon C.
VanDoren Stephen R.
Compaq Computer Corporation
Gordon Paul P.
Patel Ramesh
LandOfFree
Method and apparatus for disambiguating change-to-dirty commands does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for disambiguating change-to-dirty commands, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for disambiguating change-to-dirty commands will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1159146