Method and apparatus for disabling interrupts in a highly pipeli

Details Method and apparatus for disabling interrupts in a highly pipeli Method and apparatus for disabling interrupts in a highly pipeli

1996-11-18

1998-07-07

Treat, William M.

395734, G06F 922

Patent

active

057782202

ABSTRACT:
A method and apparatus disables and re-enables an interrupt during the execution of certain I/O and memory operations in an out-of-order processor. The out-of-order processor executes macroinstructions, wherein each macroinstruction comprises one or more microinstructions. The out-of-order processor comprises a fetch and issue unit and a reorder buffer that allows an interrupt to be serviced during the execution of the microinstructions making up any of a first class of macroinstructions. The reorder buffer, however, does not allow the interrupt to be serviced during execution of microinstructions making up a second class of macroinstructions. The second class of macroinstructions may include I/O and memory operations.

REFERENCES:
patent: 5504925 (1996-04-01), Jeffs
patent: 5664137 (1997-09-01), Abramson et al.
Torng et al.; Interrupt Handling for Out-of-Order Execution Processors; IEEE Transactions on Computers, vol. 42, No. 1; pp. 122-127, Jan. 1993.
Wang et al.; Implementing Precise Interruptions in Pipelined RISC Processors; IEEE Micro; pp. 36-43, Aug. 1993.

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