Method and apparatus for disabling and restarting clocks

Details Method and apparatus for disabling and restarting clocks Method and apparatus for disabling and restarting clocks

1993-08-12

1995-06-27

Kriess, Kevin A.

Boots, shoes, and leggings

364483, 364DIG1, 370 851, 327142, 327292, H03K 513, G01R 1900

Patent

active

054287650

ABSTRACT:
The ability to stop a clock in a CMOS peripheral device or other CMOS IC, and reliably restart it based on an asynchronous event, provides the basis for considerable power savings. In a computer system 20 an interface component 10 has a clock restart circuit 100. The restart circuit 100 includes a series of D-type CMOS flip-flops (110, 112, 118) that are initially set in their zero state. A logic OR gate 120 receives the microprocessor clock and the complimentary output of the last flip-flop to provide a reliable, restarted clock signal for the interface component 10 and its peripherals 26.

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Wakerly, John, "Designer's Guide to Synchronizers and Metastability Part I", Sep., 1987, pp. 4-8.
Wakerly, John, "Designer's Guide to Synchronizers and Metastability Part 2", Oct., 1987, pp. 4-8.

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