Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-07-18
2010-11-23
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
07840777
ABSTRACT:
A general purpose computing system comprises a novel apparatus and method for data processing. The computing system design of one application of the present invention includes an instruction pipe having a decompression circuit, a reprogrammable logic unit and a data bus. Instructions and data may be accessed via a shared bus or via a separate instruction bus and data bus. The decompression circuit accepts compressed instructions and memory management directives from the instruction bus, decompresses each instruction, and transmits the decompressed instruction to the reprogrammable logic unit. A software compiler is provided that accepts high level programming language source code and creates instructions that are coded for acceptance and execution by the reprogrammable logic unit.
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Ascenium Corporation
Chan Eddie P
Fowler Colin
Reilly Patrick
Vicary Keith
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