Pulse or digital communications – Receivers – Interference or noise reduction
Reexamination Certificate
1999-12-07
2003-10-14
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Interference or noise reduction
C375S219000
Reexamination Certificate
active
06633618
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to radio telephones and personal communicators, referred to herein generally as mobile stations, and more particularly to radio frequency (RF) receivers for these and other devices that are subject to direct current (DC) offset signals.
BACKGROUND OF THE INVENTION
A problem that arises in RF receivers is an undesirable presence of a DC offset signal. For example, an analog to digital converter (ADC) can be used to convert an input RF signal, typically a downconverted intermediate frequency (IF) signal, to a digital representation thereof, which can then be further operated on by a digital signal processor (DSP) to perform various signal processing functions. These functions can include filtering, such as Finite Impulse Response (FIR) filtering, channel estimation, decoding, and so forth.
In some conventional receivers it was known to remove or compensate the DC offset in the analog circuitry, prior to analog to digital conversion. However, this approach-can require complex circuitry, and may further require the addition of a digital to analog converter (DAC) in order to generate a suitable DC offset compensation input signal for the ADC.
Previously, it was also known to digitally remove the DC offset with an accuracy of ½ of the Least Significant Bit (LSB) of the ADC. However, if the DC offset was less than ½ LSB, then it could not be removed.
As can be appreciated, as the number of bits of resolution of the ADC is decreased, for example when it is desired to increase conversion speed while reducing cost, the magnitude of the DC offset corresponding to ½ LSB will become larger. For example, if a one volt signal is expressed in an eight bit format, a step size of the 256 possible digital values will represent about 4 millivolts, and one half of the LSB will then be about 2 millivolts. However, if the same one volt signal is expressed instead in a six bit format, a step size of the 64 possible digital values will represent about 15.5 millivolts, and one half of the LSB will be about 7.7 millivolts.
If not removed the DC offset can have a detrimental effect on the subsequent signal processing of the digitized signal. This problem can be especially vexing in code division, multiple access (CDMA) type receivers, wherein it is typically the case that not as many bits of ADC resolution are required, as compared to, for example, time division, multiple access (TDMA) receivers.
One way to reduce the magnitude of the DC offset is to specify a more expensive ADC having more bits of resolution and/or a tighter tolerance for the DC offset output from the ADC. Unfortunately, this adds cost to the device containing the ADC. In addition, the required ADC may require a longer conversion time, and may as well have a larger power consumption, which is detrimental in battery-powered equipment. Furthermore, and for the case where two signal paths need to be digitized, such as when employing a receiver providing an Inphase and a Quadrature (I/Q) output, the overall cost can be essentially doubled.
A need thus exists to provide a technique to remove a DC offset signal component that has a magnitude that is less than ½ LSB of the ADC output, thereby enabling a designer to relax the standards and requirements for the receiver ADC(s). This in turn leads to cost reductions, without sacrificing accuracy.
OBJECTS AND ADVANTAGES OF THE INVENTION
It is a first object and advantage of this invention to provide an improved mobile station, that overcomes the foregoing and other problems.
It is a further object and advantage of this invention to provide embodiments of circuitry for removing the DC offset from the output of an ADC, where the DC offset has a magnitude that is less than ½ LSB.
SUMMARY OF THE INVENTION
The foregoing and other problems are overcome and the objects of the invention are realized by methods and apparatus in accordance with embodiments of this invention.
In accordance with a first embodiment of this invention a signal path, such as receiver signal path of a mobile station, includes an analog to digital converter (ADC) for representing an input signal as n-bits, the n-bit representation including a DC offset component. The signal path may be one of an Inphase (I) or a Quadrature (Q) signal path of the mobile station. The signal path also includes a summing node having a first input for inputting the n-bit output of the ADC and a second input for inputting a k-bit representation of a DC offset component compensation value, where k=n+m, where m is a number of bits that represent a value smaller than one least significant bit (LSB) of said n-bit representation. The summing node operates to subtract the value appearing at the second input from the value appearing at the first input, and outputs a k-bit DC offset compensated value.
A filter, such as a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter, is coupled to the output of the summing node. A negative feedback path is provided from an output of the filter to the second.input of the summing node for generating the k-bit representation of the DC offset component.compensation value.
In accordance with a second embodiment of this invention the signal path includes the ADC for representing the input. signal as n-bits, the n-bit representation comprising a DC offset component. The signal path further includes a filter, such as a FIR filter or an IIR filter, having an input coupled to the output of the ADC and an output for providing a filtered k-bit representation of the ADC output, where again k=n+m, where m is a number of bits that represent a value smaller than one least significant bit (LSB) of the n-bit representation. The summing node in this embodiment has the first input coupled to the filter output for inputting the k-bit output of the filter and the second input inputs the k-bit representation of the DC offset component compensation value. The summing node operates to subtract the value appearing at said second input from the value appearing at said first input, and outputs the k-bit DC offset compensated value.
REFERENCES:
patent: 6100827 (2000-08-01), Boesch et al.
patent: 6166668 (2000-12-01), Bautista et al.
Kuiri Tapio
Walker Simon Nicholas
Wilson Alice Frances
Chin Stephen
Harrington & Smith ,LLP
Nokia Corporation
Odom Curtis
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