Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-04-23
2002-04-30
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000
Reexamination Certificate
active
06380877
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to digital to analog converters. More particularly, the invention relates to switched R-2R ladder networks.
BACKGROUND OF THE INVENTION
The functional operation of a digital to analog converter (DAC) is well known. Generally, a DAC accepts an digital input signal and converts it into an analog output signal. The digital input signal has a range of digital codes which are converted into a continuous range of analog signal levels of the analog output signal. DACs are useful to interface digital systems to analog systems. Applications of DACs include video or graphic display drivers, audio systems, digital signal processing, function generators, digital attenuators, precision instruments and data acquisition systems including automated test equipment.
There are a variety of DACs available for converting digital input signals into analog output signals depending upon the desired conversion functionality. The variations in the DACs available may have different predetermined resolutions of a digital input signal, receive different encoded digital input signals, have different ranges of analog output signals using a fixed reference or a multiplied reference, and provide different types of analog output signals. Additionally there are a number of DAC performance factors to consider such as settling time, full scale transition time, accuracy or linearity, and a factor previously mentioned, resolution.
The digital input signal is a number of bits wide that defines the resolution, the number of output levels or quantization levels and the total number of digital codes that are acceptable. If the digital input signal is m-bits wide, there are 2
m
output levels and 2
m−1
steps between levels. The digital input signals may be encoded in straight binary, two's complement, offset binary, grey scale code, binary coded decimal or other digital coding. The range of analog output signal values usually depend upon an analog reference. The analog reference may be internally generated but is usually externally provided for precision. The analog output signal range may be proportional to the digital input signal over a fixed analog reference level as in a fixed reference DAC. Alternatively, the analog output signal may be the product of a varying input analog reference level and the digital code of the digital input signal as in multiplying DACs. The analog output signal may be unipolar ranging in either positive values or negative values or it may be bipolar ranging between both positive and negative output values. The analog output signal may be an analog voltage signal or an analog current signal.
Additionally, the type of electronic circuitry used to form a DAC varies as well. Bipolar junction transistor (BJT) technology, metal oxide semiconductor (MOS) technology or a combination thereof are used to construct DACs. BJT technology may be PNP technology with PNP transistors or NPN with NPN transistors or both, while MOS technology may be PMOS with P-channel field effect transistors (PFET), NMOS with N-channel field effect transistors (PFET) or CMOS technology having both PFETs and NFETs.
Referring now to
FIG. 1A
, a block diagram of a DAC
100
has a digital input signal DIN
101
, a positive analog supply voltage level AVref+
104
, and a negative analog supply voltage level AVref−
105
in order to generate an analog voltage output signal AVout
110
. Alternatively DAC
100
can generate an analog current output signal with minor changes to its circuit configuration. For simplicity in discussion consider DAC
100
to be a fixed reference DAC such that the output voltage range of AVout
110
is a function of DIN
101
and the range of voltage is defined by the predetermined voltage levels of AVref+
104
and AVref−
105
. DIN
101
is m bits wide. The predetermined value of m represents the range of decimal numbers that DIN
101
will represent. The selected circuitry for DAC
100
varies depending upon a number of factors including power supply inputs and desired parameters of input and output signals. As illustrated in
FIG. 1A
, DAC
100
includes a signal converter
112
and an amplifier or buffer
114
. Some forms of DACs, specifically current output DACs, may not include the buffer
114
and require external amplification. Signal converter
112
converts DIN
101
into a form of analog signal, VLADR
102
, which is input to buffer
114
. Buffer
114
buffers the analog signal VLADR
102
generated by the signal converter
112
from a load that may be coupled to AVout
110
. The signal converter
112
includes a switched R-2R ladder
116
and a switch controller
118
. Switch controller
118
controls switches within the switched R-2R ladder
116
to cause it to convert the value of DIN
101
into an analog signal.
As previously discussed, there are a number of DAC performance factors to consider including a DAC's accuracy or linearity. Referring now to
FIGS. 1B and 1C
, graphs of bipolar output voltages for AVout
110
and unipolar output voltages for AVout
110
as a function of the digital input signal DIN
101
are illustrated. Transfer curves
120
-
121
represent the ideal transfer characteristics of a DAC for converting DIN into AVout. Transfer curves
122
-
123
represent the actual measured transfer characteristics of a DAC for converting DIN into AVout. The difference between the ideal transfer curves
120
-
121
and the actual transfer curves
122
-
123
is the integral linearity of a DAC. If a change in an analog voltage reference level is required to establish a zero point or a midpoint of the conversion range it is referred to as an offset voltage. Differential linearity is the linearity between code transitions measuring the monotonicity of a DAC. If increasing code values of DIN results in increasing values of AVout, the DAC is monotonic, and if not, the DAC has a conversion error and is not monotonic. The linearity of a DAC is very important for accurate conversions and is usually specified in units of least significant bits (LSB) of the m-bits of DIN. Linearity of a DAC can vary over temperature, voltages, and from circuit to circuit. Additionally, DAC linearity becomes more important as the predetermined DAC resolution is increased where the value of m is larger and additional digital codes are desired to be converted. Furthermore, as the analog voltage reference level range between AVref+
104
and AVref−
105
may be increased to accommodate additional resolution, it is desirable to maintain linearity in a DAC.
Referring now to
FIG. 2A
, a prior art switched R-2R ladder
116
is illustrated. The switched R-2R ladder
116
is a 4 bit inverted R-2R ladder to provide an analog voltage output signal but may be easily expanded to m-bits with the addition of other intermediate R-2R switch legs and additional switch control lines. Alternatively, a non-inverted R-2R ladder could be used to provide an analog current output signal. Signals DBn/DBp
201
are selectively controlled by the switch controller
118
in order to generate an analog voltage output signal VLADR
102
. DBn/DBp
201
switches ON and OFF NFETs
211
-
214
and PFETs
216
-
219
in order to change the voltage division of the R-2R resistor network between AVref+
104
and AVref−
105
and VLADR
102
. Inverters
246
-
249
generate the inverter polarity of the switch control lines D
4
Bp-D
1
Bp
241
-
244
to control the NFETs
236
-
239
to form fully complementary switches with PFETs
216
-
219
. NFET
211
and PFET
216
/NFET
236
represent the MSB of the DAC and can couple {fraction (8/16+L )} of the reference voltage range to VLADR
102
. NFET
212
and PFET
217
/NFET
237
can couple {fraction (4/16+L )} of the reference voltage range to VLADR
102
. NFET
213
and PFET
218
/NFET
238
can couple {fraction (2/16+L )} of the reference voltage range to VLADR
102
. NFET
214
and PFET
219
/NFET
239
represent the LSB of the DAC and can couple {fraction (1/16+L )} of the reference volt
Castaneda David
Fang Gary G.
Rahim Chowdhury F.
Blakely , Sokoloff, Taylor & Zafman LLP
Jean-Pierre Peguy
Jeanglaude Jean Bruner
Maxim Integrated Products Inc.
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