Coded data generation or conversion – Converter compensation
Reexamination Certificate
2011-07-26
2011-07-26
Young, Brian (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S161000
Reexamination Certificate
active
07986253
ABSTRACT:
An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code.
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“A 1.2V 10b 20MSSample/s Non-Binary Successive Approximation ADC in 0.13 m CMOS”, F. Kuttner, ISSCC Dig. Tech. Papers, pp. 176-777, Feb. 2002.
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“SAR ADC Architecture with Digital Error Correction”, Masao Hotta, IEEJ International Analog VLSI Workshop, 2006.
Cho Sang-Hyun
Ryu Seung-Tak
Sung Barosaim
Bacon & Thomas PLLC
Korea Advanced Institute of Science and Technology
Young Brian
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