Method and apparatus for digital delay locked loop circuits

Details Method and apparatus for digital delay locked loop circuits Method and apparatus for digital delay locked loop circuits

2000-08-30

2002-03-19

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000, C327S161000, C327S271000, C375S376000, C331SDIG002, C331S00100A

Reexamination Certificate

active

06359482

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuitry for generation of periodic signals such as dock signals. More specifically, the present invention relates to a delay line circuit for register controlled digital delay locked loop (DDLL) circuits which use fewer gates and have improved performance.
2. Description of the Related Art
Many high speed electronic systems possess critical timing requirements which dictate the need to generate a periodic clock wave form that possesses a precise time relationship with respect to some reference signal. The improved performance of computing integrated circuits (ICs) and the growing trend to include several computing devices on the same board present a challenge with respect to synchronizing the time frames of all the components.
While the operation of all components in the system should be highly synchronized, i.e., the maximum skew or difference in time between the significant edges of the internally generated clocks of all the components should be minute, it is not enough to feed the reference clock of the system to all the components. This is because different chips may have different manufacturing parameters which, when taken together with additional factors such as ambient temperature, voltage, and processing variations, may lead to large differences in the phases of the respective chip generated clocks.
Conventionally, synchronization is achieved by using DDLL circuits to detect the phase difference between clock signals of the same frequency and produce a digital signal related to the phase difference. By feeding back the phase difference-related signal to control a delay line, the timing of one clock signal is advanced or delayed until its rising edge is coincident with the rising edge of a second clock signal.
The operation of conventional DDLLs is shown in
FIGS. 1 and 2
. In
FIG. 1
, clock input buffer
104
, delay lines
101
,
102
, and data output buffer
109
constitute an internal clock path. Delay line
101
is a variable delay generator with a logic-gate chain. A second delay line
102
is connected to replica circuits
108
, which emulate the internal clock path components. Replica circuits
108
include dummy output buffer
110
, with dummy load capacitance
111
and dummy clock buffer
107
. The dummy components and second delay line
102
constitute a dummy clock path having exactly the same delay time as the internal clock path. Shift register
103
is used for activating a number of delay elements in both delay lines based on a command generated by phase comparator
106
.
Phase comparator
106
compares the dummy clock and the external clock phases which differ by one cycle. This comparison is illustrated in
FIGS. 2A
,
2
B,
2
C, and
2
D. External dock signal
200
is divided down in divider
105
to produce divided-down external signal
201
. Signal
202
is the signal at the output of dummy delay line
102
. Signal
203
, which is generated inside phase comparator
106
, is a one delay unit delayed output dummy line signal
202
. If both signals
202
and
203
go high before
201
goes low, this means that the output clock is too fast and phase comparator
106
outputs a shift left (SL) command to shift register
103
, as illustrated in FIG.
2
B. Shift register
103
shifts the tap point of delay lines
102
and
101
by one step to the left, increasing the delay. Conversely, if both signals
202
and
203
go high after
201
goes low, this means that the output clock is too slow and phase comparator
106
outputs a shift right (SR) command to shift register
103
, as illustrated in FIG.
2
D. Shift register
103
shifts the tap point of delay lines
102
and
101
by one step to the right, decreasing the delay. If
201
goes low between the time
202
and
203
go high, the internal cycle time is properly adjusted and no shift command is generated, as illustrated in FIG.
2
C. The output of the internal clock path in this case coincides with the rising edge of the external clock and is independent of external factors such as ambient temperature and processing parameters.
A schematic diagram of a conventional Vernier Delay Line (VDL) circuit
300
used for the stages of delay line
101
of
FIG. 1
is shown in FIG.
3
. The circuit
300
of
FIG. 3
consists of a series of n delay stages, each stage consisting of three NAND gates
305
,
306
and
307
and two inverters
310
,
311
. The unit delay for stage
301
of upper delay line
302
consists of NAND gate
305
and inverter
310
. The upper delay line
302
and tower delay line
303
are connected through NAND switch
306
whose transistor gates become the load for the upper delay line
302
. Shift register
315
provides a signal to open or close NAND switch
306
. The delay of the upper delay line
302
slightly exceeds that of the lower delay line
303
. This delay difference becomes the unit delay time of the VDL circuit
300
.
FIG. 3A
illustrates in block diagram form the functioning of the VDL circuit
300
of FIG.
3
. Each unit delay
350
,
351
,
352
,
353
,
354
in upper delay line
302
has a delay time of 1.2 td, and each unit delay
360
,
361
,
362
,
363
,
364
in lower delay line
303
has a delay time of td, where td is the unit delay time of the conventional delay generator. The additional 0.2 td delay of the upper delay line in this example is due to the gate loading from the NAND switches. These unit delays
350
-
354
and
360
-
364
are serially connected through switches
370
,
371
,
372
,
373
, and
374
. If only switch
370
closes, the VDL generates a delay of 5 td from IN node
340
to OUT node
399
. Similarly, if switch
371
closes, the VDL generates a delay time of 5.2 td from IN node
340
to OUT node
399
. Thus, the VDL circuit
300
is capable of generating a delay of every 0.2 td delay time.
Conventional delay lines of DDLLs, however, suffer from numerous drawbacks. One such drawback is that the resolution, i.e., the delay per stage, of the delay line is dependent upon the number of gates for each unit delay of the stage. The larger the number of gates in each unit delay, the larger the unit delay time td. Although the circuit shown in
FIG. 3
can generate a delay of every 0.2 td, the resolution is limited by the value of td. The larger the value of td, the lower the resolution possible.
In addition to providing poor resolution, a high value for the unit delay time td can cause problems when the DDLL is placed in a state of minimum delay. A state of minimum delay occurs when the delay between the input and output clock signals is as close to zero as allowed by the parameters of the delay line, i.e., the smallest delay as allowed by the unit delay time td. In this case, if the DDLL attempts to decrease the delay, such decrease would be impossible because the delay line is already at minimum delay. Each unit delay of the delay line shown in
FIG. 3
consists of one NAND gate and one inverter. The unit delay time for each unit delay having this construction is approximately 200-300 picoseconds. The minimal delay of the delay line
300
is thus limited to 200-300 picoseconds, without the possibility of decreasing the unit delay time below that time. Thus, the resolution of the delay line, determined by the unit delay time, is limited by the number of gates in each unit delay.
A further drawback of conventional DDLL circuits is the space required to layout the circuitry of the DDLLs. Each stage of the delay line consists of three NAND gates and two inverters for a total of five gates. Each stage could be replicated 50-100 times to target a typical clock input frequency of 100 MHz. This extensive amount of circuitry occupies a significant amount of space within a semiconductor circuit.
Yet another drawback of conventional DDLL circuits is that they are inherently inaccurate due to asymmetries in the delay line design. Each stage of the delay line consists of three NAND gates and two inverters. Unless the pull-up and pull-down times of the transistors forming the

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