Pulse or digital communications – Synchronizers – Network synchronizing more than two stations
Reexamination Certificate
2006-04-04
2006-04-04
Ha, Dac V. (Department: 2634)
Pulse or digital communications
Synchronizers
Network synchronizing more than two stations
C375S372000, C370S506000
Reexamination Certificate
active
07023942
ABSTRACT:
Synchronization and desynchronization of a data signal transported in a synchronous frame across a synchronous communications network, such as SONET/SDH, reduces waiting-time jitter. A timing estimate (F) indicative of a relationship between a data rate (f1) of the data signal and a reference frequency (f2) of the synchronous communications network is calculated and communicated through the synchronous communications network, for example in the Synchronous Payload Envelope of a SONET frame. The data signal is recovered using a desynchronizer Phase-Locked Loop steered by the timing estimate (F). The timing estimate (F) can be any one or more of: a ratio between the data rate (f1) and the reference frequency (f2); a difference between the data rate (f1) and the reference frequency (f2); and a phase difference between a recovered data clock signal associated with the data rate (f1) and a reference clock signal associated with the reference frequency (f2).
REFERENCES:
patent: 5497405 (1996-03-01), Elliott et al.
patent: 6415006 (2002-07-01), Rude
patent: 6535567 (2003-03-01), Girardeau, Jr.
patent: 6674771 (2004-01-01), Taniguchi
patent: 6819725 (2004-11-01), Oliver et al.
patent: 0248551 (1987-09-01), None
patent: 1067722 (2001-10-01), None
patent: WO 96 39762 (1996-12-01), None
Lau R C et al: “Synchronous Techniques for Timing Recovery in Bisdn” IEEE Transactions on Communications, IEEE Inc. New York, US, vol. 43, No. 2/4, Part 3, Feb. 1, 1995, pp. 1810-1818, XPOOO5O5653 ISSN: OO9O-6778, p. 1, right-hand col. line 35-line 44, p. 2, right-hand col. line 21-line 29, p. 2, right-hand col. line 42, p. 3, left-hand col. line 10, p. 3 right-hand col. line 3-line 25, p. 4, left-hand col. 26-line 31, p. 4, right-hand col. line 3-line 11, figs. 3, 5-7.
Duttweiler D L: “Waiting Time Jitter” Bell System Technical Journal, American Telephone and Telegraph Co. New York, US, vol. 51, No. 1, Jan. 1972, pp. 165-207, XPOOO798920 cited in the application p. 1-6.
Mulvey M et al: “Timing Issues of Constant Bit Rate Services Over ATM” BT Technology Journal, BT Laboratories, GB, vol. 13, No. 3, Jul. 1, 1995, pp. 35-45, XPOOO543496 ISSN: 1358-3948 paragraphs 03.0!-03.2!.
Nawrocki R et al: “Waiting Time Jitter Reduction by Fill Locking” Electronics Letters, IEE Stevenage, GB, vol. 26, No. 16, Aug. 2, 1990 pp. 1227-1228, XPOOO1O8212, ISSN: 0013-5194, the whole document.
Gagnon Ronald J.
Roberts Kim B.
Shields James A.
Ha Dac V.
Nortel Networks Limited
Ogilvy Renault LLP
Roy Matthew M.
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