Method and apparatus for differential signal detection

Amplifiers – With semiconductor amplifying device – Including differential amplifier

Reexamination Certificate

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Details

C330S069000

Reexamination Certificate

active

06781465

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This disclosure pertains generally to a detection circuit and, in particular, to a method and apparatus for detecting differential signal levels using a circuit having a self-induced DC offset.
2. Description of the Related Art
FIG. 1
is a circuit diagram of a conventional differential signal detection circuit
100
described in U.S. Pat. No. 6,194,965 B1 issued to Kruczkowski et al. on Feb. 27, 2001 (hereafter the '965 patent) and assigned to Cypress Semiconductor Corp.
The circuit
100
includes a differential amplifier stage
102
and an output circuit
104
. The output circuit
104
includes a differential buffer
142
. The differential amplifier stage
102
includes a logic circuit
130
composed of a differential OR gate
132
.
The differential amplifier stage
102
of circuit
100
uses four matched differential amplifiers. One of the four matched differential amplifiers is composed of resistors R
1
, R
2
, and R
5
; field-effect transistors (FETs) Q
1
and Q
2
, and a current source
12
to bias the transistors Q
1
and Q
2
. The other three matched differential amplifiers in differential amplifier stage
102
have the same structure but are made from other components. The top two of the matched differential amplifiers make up a pair circuit
106
and the other two make up a pair circuit
108
.
The circuit
100
requires external references VCM_HI and VCM_LO, to perform the signal detect process. The current source
11
and the resistors R
5
, R
6
create common mode voltage VCM_HI in the pair circuit
106
, while the current source
15
and the resistors R
11
, R
12
create another common mode voltage VCM_LO in the pair circuit
108
. Four comparisons are made to perform the signal detect process in circuit
100
, one for each matched differential amplifier. Signals taken from nodes Z_N, Z_P, Y_N, and Y_P from the pair circuits
106
and
108
form the inputs to the differential OR gate
132
.
Embodiments of the invention improve upon the conventional circuit by eliminating the need for the common mode voltages VCM_HI and VCM_LO, which decreases noise susceptibility. Embodiments of the invention also improve upon the conventional circuit by reducing circuit area and power consumption.
SUMMARY OF THE INVENTION
Embodiments of the invention provide a differential signal detection device and an indication circuit. A particular embodiment includes at least two differential amplifiers that are purposely mismatched so that one leg of each amplifier is different than the other leg in the same amplifier. This gives the differential amplifiers a non-symmetric characteristic.
Other embodiments of the invention provide a data bus signal level detection system. The system includes first and second input terminals coupled to first and second signal lines of a data bus, and first and second differential amplifiers coupled to both the first and second input terminals. An indication circuit produces signals based upon the output from the first and second differential amplifiers. The differential amplifiers each have a first leg with a first set of components and second leg with a second set of components, but the first and second set of components do not match.
A method for detecting differential signals is also provided. First and second differential input signals are applied to purposely mismatched differential amplifiers. The differential amplifiers are mismatched because the leg of one branch of the amplifier is non-symmetric when compared to the other leg of the amplifier. The output signals from the differential amplifiers are then compared in a logic circuit that produces an output based on that comparison.


REFERENCES:
patent: 4377789 (1983-03-01), Hoover
patent: 5663680 (1997-09-01), Nordeng
patent: 5703532 (1997-12-01), Shin et al.
patent: 5939904 (1999-08-01), Fetterman et al.
patent: 6188282 (2001-02-01), Montalvo
patent: 6194965 (2001-02-01), Kruczkowski et al.

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