Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-08-17
2004-01-20
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S118000, C438S617000, C228S180500
Reexamination Certificate
active
06680219
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits. Particularly, the present invention relates to the stacking of dies on an integrated circuit substrate.
2. Description of the Related Art
Integration at the silicon level can be expensive. Typically, the number of transistors on a die can be increased by decreasing the size of the transistors. However, manufacturing an integrated circuit (IC) package that must be comprised of different types of circuits (e.g., analog, digital) can pose various problems.
For example, a problem might be that one circuit is manufactured with 0.25 &mgr;m technology while another circuit is manufactured with 0.18 &mgr;m technology. The integrated circuit designer must either manufacture two separate integrated circuits or try to design the 0.25 &mgr;m technology circuit using the 0.18 &mgr;m technology. Neither solution is acceptable since the first increases the size and cost of an electronic product manufactured with multiple integrated circuit packages while the second solution requires additional time and cost to design the new circuit.
An additional problem with combining circuits is the cost associated with designing the different circuits on one die. This requires redesigning the die and designing additional processes to manufacture the die.
One solution for combining circuits in an IC-package is to stack separate dies comprising different technologies. Such a die stacking process would be limited to one die on top of another due to the requirement of electrically coupling the dies to bond fingers on the substrate. Dies and substrates are currently manufactured with their pads and bond fingers on their respective peripheries such that bonding wires from the pads to the bonding fingers surround the die on most sides.
Another difficulty in die stacking is electrically coupling the circuit of the upper die to the circuit of the lower die without going to the substrate first. This would require additional bond fingers on an already densely laid-out substrate. There is a resulting need for a more efficient and less expensive method for increasing the circuit density of an IC-package by die stacking.
SUMMARY OF THE INVENTION
The die-stacking method and integrated circuit (IC) package apparatus of the present invention enable an IC-package to be manufactured that comprises multiple circuit technologies. The die-stacking method integrates at the IC-package level by the stacking and coupling of multiple dies to produce an integrated circuit apparatus that is the same size as a non-stacked integrated circuit but has greater functionality.
The IC package of the present invention is possible by grouping the bond fingers in a location of the substrate that is offset from the center of the substrate. This permits additional dies to be added to the substrate laterally from a first die that is positioned in the offset location.
The lateral dies and the stacked dies each have their pads grouped in a predetermined area that corresponds with specially grouped pads on the first die. The dies that are positioned laterally from the first die are coupled directly to the first die with bond wire bridges that span lower bond wires. The stacked dies are electrically coupled to the first die with bond wires to a group of the specially grouped pads.
The method for constructing an integrated circuit apparatus comprises generating a substrate with a plurality of bond fingers. A lower die is coupled to the substrate. This coupling comprises both mechanically attaching the die to the substrate and electrically coupling the die circuitry to the bond fingers with bond wires.
An upper die is mechanically attached to the lower die. The upper die is then electrically coupled to the substrate such that pads on the upper die are coupled to the plurality of bond fingers. The upper die may be electrically coupled to the lower die with additional bond wires
If a second lower die is attached to the substrate, a bridge of bond wires electrically couples the upper die to the second lower die. A bond wire bridge may also electrically couple the second lower die to the first lower die.
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patent: 5552966 (1996-09-01), Nagano
patent: 6014586 (2000-01-01), Weinberg et al.
patent: 6407456 (2002-06-01), Ball
patent: 6431456 (2002-08-01), Nishizawa et al.
patent: 1061579 (2000-12-01), None
patent: 4-99056 (1992-03-01), None
Irzhann Fifin
Reyes Edward
Brown Charles D.
Chambliss Alonzo
Pappas George C.
Talbott David L.
Wadsworth Philip R.
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