Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification
Reexamination Certificate
2011-06-21
2011-06-21
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Analysis and verification
C716S051000, C716S055000, C382S149000, C700S121000
Reexamination Certificate
active
07966583
ABSTRACT:
Embodiments of the present invention provide systems and techniques for determining the effect of process variations. During operation, the system can receive a layout which includes multiple instances of a pattern. Next, the system can correct the pattern instances using different photolithography process models which model the photolithography process at different exposure and focus conditions. Next, the corrected layout can be printed on a wafer. The system can then perform electrical tests on the wafer, or it can measure the critical dimensions of the features on the wafer. The yield loss or the exposure-focus matrix can then be generated by using the test data or the measurement data.
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Huynh, B. et al., “Calibrated Exposure and Focus Test Patterns for Characterization of Optical Projection Printing”, Microelectronic Engineering 9 (1989), pp. 79-82.
Van Adrichem Paulus J. M.
Zhang Yunqiang
Park Vaughan Fleming & Dowler LLP
Sahasrabuddhe Laxman
Synopsys Inc.
Whitmore Stacy A
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