Method and apparatus for determining signal line interconnect wi

Details Method and apparatus for determining signal line interconnect wi Method and apparatus for determining signal line interconnect wi

1997-10-13

2000-03-14

Teska, Kevin J.

39550035, 39550011, 39550013, G06F 1750

Patent

active

060383836

ABSTRACT:
A method for designing and fabricating an integrated circuit is disclosed. Signal line interconnect widths are determined by performing an electromigration analysis on a trial layout of the integrated circuit. A representative circuit for an integrated circuit is designed and a trial layout is created that includes a plurality of nets. A preprocessor 505 eliminates nets that do not need further validation. An extraction process 510 generates an RC network representation of each remaining net that is to be validated to form a distributed load simulation model. Distributed capacitance and resistance of signal lines is included with load capacitance of receivers to provide an accurate profile of current flow. A profile of current flowing in the signal line of each net is determined by simulating the operation of each net using simulator 517. Peak current, RMS current and average current is determined. Post processor 520 determines if electromigration parameters are violated based on the current profile determined for each net. Widths for various segments of signal lines in the various nets are selected to be greater than or equal to a minimum width determined by post processor 520.

REFERENCES:
patent: 5349542 (1994-09-01), Brasen et al.
patent: 5404310 (1995-04-01), Mitsuhashi
patent: 5410490 (1995-04-01), Yastrow
patent: 5446676 (1995-08-01), Huang et al.
patent: 5535370 (1996-07-01), Raman et al.
patent: 5537328 (1996-07-01), Ito
patent: 5553008 (1996-09-01), Huang et al.
patent: 5581475 (1996-12-01), Majors
patent: 5598348 (1997-01-01), Rusu et al.
patent: 5648910 (1997-07-01), Ito
patent: 5737580 (1998-04-01), Hathaway et al.
patent: 5768145 (1998-06-01), Roethig
patent: 5828580 (1998-10-01), Ito
patent: 5831867 (1998-11-01), Aji et al.
patent: 5835380 (1998-11-01), Roethig
patent: 5872952 (1999-02-01), Tuan et al.
Bakoglu, H.B., Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Pub. Co., pp. 53-55, no date.
Black, J.R., Electromigration Failure Modes in Aluminum Metallization for Semiconductor Devices, Proc. IEEE, vol. 57, No. 9, Sep. 1969, pp. 1587-1594.
Ting, L.M., et al., AC Electromigration Characterization and Modeling of Multilayered Interconnects, Proc. Of the 31.sup.st Annual Int'l Reliability Physics Symposium, 1993, pp. 311-316.
Maiz, J.A., Characterization of Electromigration Under Bidirectional (BC) and Pulsed Unidirectional (PDC) Currents, Proc. Of the 27.sup.th Annual Int'l Reliability Physics Symposium, 1989, pp. 220-228.
Scarpulla, John, et al., Reliability of Metal Interconnect After a High-Current Pulse, IEEE Electron Device Letters, vol. 17, No. 7, Jul. 1996, pp. 322-324.
Marguia, J.E., et al., Short-Time Failure of Metal Interconnect Caused by Current Pulses, IEEE Electron Device Letters, vol. 14, No. 10, Oct. 1993, pp. 481-483.

Affiliated with

Also associated with

Rating

Method and apparatus for determining signal line interconnect wi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for determining signal line interconnect wi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for determining signal line interconnect wi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-177448