Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-08-28
2007-08-28
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200
Reexamination Certificate
active
11297527
ABSTRACT:
A method of automatically determining a sensing timing in a page buffer of a NAND flash memory device is disclosed, which includes the steps of discharging a first reference bit line, discharging a second reference bit line, determining a first control signal and determining a second control signal. To perform the method, an apparatus of automatically determining a sensing timing in a page buffer of a NAND flash memory device is also disclosed. The apparatus includes a first reference bit line, a first current sink, a first reference page buffer, the second reference bit line, a second current sink and a second reference page buffer. The first reference bit line is coupled to the first current sink and the first reference page buffer at both ends thereof. The second reference bit line is coupled to the second current sink and the second reference page buffer at both ends thereof.
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Kang-Deog Suh et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995.
Egbert Law Offices
Elite Semiconductor Memory Technology Inc.
Phung Anh
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