Method and apparatus for determining phase locked loop jitter

Details Method and apparatus for determining phase locked loop jitter Method and apparatus for determining phase locked loop jitter

2000-09-26

2002-08-27

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

C324S141000, C324S142000, C327S156000

Reexamination Certificate

active

06441602

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to testing integrated circuits, and, more particularly, to a method and apparatus for measuring jitter in phase locked loops.
BACKGROUND OF THE INVENTION
Phase locked loops (PLLs) have been used for clock generation in microprocessors. One advantage to using a PLL is the multiplication of the reference clock frequency. The PLL can generate an output clock or multiple output clocks, that are a multiple of the reference clock frequency, with each of the PLL clocks being phase aligned.
The advantages of a PLL become lost if the PLL experiences “jitter” or variation of the phase alignment. Thus, there exist test methods to detect the presence of PLL jitter. PLL jitter is often measured deterministically, finding a distribution of jitter and computing the standard deviation to obtain a 3 sigma jitter number. While this is an acceptable test method for most specifications, a single PLL phase variation event can cripple high speed integrated circuits. Thus, there is a need for an absolute measurement of PLL jitter rather than a statistical one.
BRIEF SUMMARY OF THE INVENTION
An exemplary embodiment of the invention is a method for evaluating jitter of a phase locked loop circuit generating a phase locked loop output signal. The method includes generating a test initiate signal and generating a trigger signal in response to the test initiate signal. The trigger signal is synchronized with the phase locked loop output signal. A disturbance signal is generated to induce jitter in the phase locked loop output signal. The jitter in the phase locked loop output signal is then evaluated.


REFERENCES:
patent: 3983498 (1976-09-01), Malek
patent: 6005872 (1999-12-01), Bassi
patent: 6185510 (2001-02-01), Inoue
Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops, Keith A. Jenkins and James P. Eckhardt, IEEE Design & Test of Computers, Apr.-Jun. 2000, pp. 6-8, 88-93.

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