Method and apparatus for determining error location

Details Method and apparatus for determining error location Method and apparatus for determining error location

1993-06-29

1995-10-31

Trammell, James P.

Excavating

371 391, 371 381, H03M 1300

Patent

active

054636426

ABSTRACT:
A circuit for determining locations of the errors that occur during data storage tests each possible error location using an error location polynomial. Accumulating registers of a set of multiplier accumulators are loaded with the components of the error location polynomial at the start of each 120-byte word to be tested. The output signals of the accumulating registers are transferred to an XOR checksum circuit. If the output of the XOR checksum circuit is determined to be zero, the current byte of the tested word is considered to be an error location. An external clock signal corresponding to the consecutive bytes to be tested saves the outputs of the unary multipliers for multiplying by the Galois field elements .alpha..sup.123 -.alpha..sup.131, through a feedback loop to the multiplier accumulating registers.

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patent: 5136592 (1992-08-01), Weng
patent: 5170399 (1992-12-01), Cameron et al.

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