Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-03-08
2011-03-08
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S103000, C716S104000, C327S161000, C703S014000
Reexamination Certificate
active
07904859
ABSTRACT:
Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time, and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described.
REFERENCES:
patent: 4128201 (1978-12-01), Barron et al.
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5721890 (1998-02-01), Langendorf
patent: 5850537 (1998-12-01), Selvidge et al.
patent: 5878221 (1999-03-01), Szkopek et al.
patent: 5943490 (1999-08-01), Sample
patent: 5990734 (1999-11-01), Wright et al.
patent: 6002861 (1999-12-01), Butts et al.
patent: 6052748 (2000-04-01), Suominen et al.
patent: 6072346 (2000-06-01), Ghahremani
patent: 6618839 (2003-09-01), Beardslee et al.
patent: 6691301 (2004-02-01), Bowen
patent: 6694464 (2004-02-01), Quayle et al.
patent: 6701491 (2004-03-01), Yang
patent: 6727740 (2004-04-01), Kirsch
patent: 6823497 (2004-11-01), Schubert et al.
patent: 6904576 (2005-06-01), Ng et al.
patent: 7007254 (2006-02-01), Borkovic et al.
patent: 7072818 (2006-07-01), Beardslee et al.
patent: 7213216 (2007-05-01), Ng et al.
patent: 7398445 (2008-07-01), Ng et al.
patent: 7617470 (2009-11-01), Dehon et al.
patent: 2002/0156614 (2002-10-01), Goode
patent: 2004/0222857 (2004-11-01), Adkisson
patent: 2005/0081113 (2005-04-01), Beard et al.
patent: 2006/0022724 (2006-02-01), Zerbe et al.
patent: 2006/0062341 (2006-03-01), Edmondson et al.
patent: 2006/0190860 (2006-08-01), Ng et al.
patent: 2006/0259834 (2006-11-01), Ng et al.
patent: 2008/0098339 (2008-04-01), Chan
patent: 2008/0301601 (2008-12-01), Ng et al.
patent: 2008/0313578 (2008-12-01), Maixner et al.
patent: 2008/0313579 (2008-12-01), Larouche et al.
patent: 1 441 296 (2004-07-01), None
patent: 10-0710972 (2007-04-01), None
patent: 10-0767957 (2007-10-01), None
patent: 10-0812938 (2008-03-01), None
PCT Invitation to Pay Additional Fees, PCT/US2008/005989, Oct. 13, 2008, 6 pages.
PCT International Search Report and Written Opinion, PCT/US2008/005989, Dec. 29, 2008, 23 pages.
PCT Invitation to Pay Additional Fees, PCT/US2008/006011, Sep. 30, 2008, 6 pages.
PCT International Search Report and Written Opinion, PCT/US2008/006009, Sep. 25, 2008, 10 pages.
PCT Invitation to Pay Additional Fees, PCT/US2008/006012, Oct. 16, 2008, 6 pages.
Chuang, Chin-Lung, et al., “A Snapshot Method to Provide Full Visibility for Functional Debugging using FPGA,” Proceedings of the 13th Asian Test Symposium, IEEE Computer Society, Nov. 15, 2004, 6 pages.
Chuang, Chin-Lung, et al., “Hybrid Approach to Faster Functional Verification with Full Visibility,” IEEE Design & Test of Computers, Advances in Functional Validation through Hybrid Techniques, vol. 24, No. 2, Mar. 1, 2007, pp. 154-162.
Koch, Gernot, et al., “Debugging of Behavioral VHDL Specifications by Source Level Emulation,” Design Automation Conference, IEEE Computer Society, Sep. 18, 1995, pp. 256-261.
PCT International Search Report and Written Opinion, PCT/US2008/006012, Jan. 14, 2009, 21 pages.
PCT International Search Report and Written Opinion, PCT/US2008/006011, mailing date Mar. 17, 2009, 21 pages.
Larouche Mario
Maixner Richard C.
McElvain Kenneth S.
Ng Chun Kit
Blakely , Sokoloff, Taylor & Zafman LLP
Levin Naum B
Synopsys Inc.
Szepesi Judith A.
LandOfFree
Method and apparatus for determining a phase relationship... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for determining a phase relationship..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for determining a phase relationship... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2668621