Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By presence or absence pulse detection
Reexamination Certificate
2000-12-18
2004-05-18
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By presence or absence pulse detection
C327S020000, C327S065000, C327S089000
Reexamination Certificate
active
06737892
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to clock signals and clocking circuitry in a digital system. More specifically, the present invention relates to a method and an apparatus for detecting valid clock signals at a clock receiver circuit.
2. Related Art
New systems for transferring data between computer system components have recently been developed to keep pace with processor clock speeds that continue to increase at an exponential rate. New “source synchronous” data transfer systems send a clock signal from a transmitting circuit to a receiving circuit along with accompanying data bits. This clock signal is used to clock the accompanying data bits into the receiving circuit. Note that using a source synchronous data transmission system allows the transmitting circuit and the receiving circuit to reside in different power and clock domains.
Unfortunately, sending a clock signal along with the data can make the data transfers susceptible to interruptions in the clock signal. Interruptions in the clock signal can occur in a number of ways. For example, interruptions in the clock signal can arise when a board is removed from a computer system, either accidentally or during a hot swap operation; when a clock wire is broken; or when power is interrupted.
Interruptions in the clock signal can cause a number of problems. If a clock line for some reason becomes disconnected, differential noise at the clock receiver can cause spurious oscillations in the received clock signal. This can cause invalid data values to be latched into the receiving circuit. Moreover, if these spurious oscillations occur high frequencies, the rapid switching of the associated clocking circuitry can cause power consumption at the receiving circuit to be extremely high, which can potentially damage the receiving circuitry.
Some existing system employ a clock receiver circuit with input hysteresis to prevent a clock receiver from misinterpreting noise as a valid clock signal. However, clock receivers with input hysteresis can introduce phase errors, which can adversely affect data transfer performance. Furthermore, conventional receiver circuits with input hysteresis cannot detect an interrupted clock signal, and consequently cannot generate a logic signal to indicate an interrupted clock signal. Hence, these system cannot take actions to mitigate the effects of an interrupted clock signal.
What is needed is a method and an apparatus for detecting an interrupted clock signal at a clock receiver circuit.
SUMMARY
One embodiment of the present invention provides a system for detecting a valid clock signal at a clock receiver. The system operates by receiving a clock signal at the clock receiver, and directing the clock signal into a control input of a voltage-controlled variable resistor. Next, the system uses the voltage-controlled variable resistor to control a first current. A current mirror is then employed to create a second current from the first current. This second current passes through a resistor to produce a control voltage, which is amplified to produce a validity signal indicating whether or not the clock signal is valid.
In one embodiment of the present invention, the system additionally uses at least one capacitor to filter out periodic fluctuations in the validity signal.
In one embodiment of the present invention, the clock signal is a differential clock signal that includes a first clock signal and a second clock signal. In this embodiment, the voltage-controlled variable resistor includes a first variable resistor in parallel with a second variable resistor, wherein the first clock signal is directed into a control input of the first variable resistor, and the second clock signal is directed into a control input of the second variable resistor.
In one embodiment of the present invention, the current mirror includes a first P-type transistor with a drain coupled to V
DD
, and a source and a gate coupled to a first end of the voltage-controlled variable resistor, so that the first current flows through the first P-type transistor. The current mirror also includes a second P-type transistor with a drain coupled to V
DD
, a gate coupled to the first end of the voltage-controlled variable resistor, and a source coupled to a first terminal of the control voltage and then to ground through a first resistor. In this embodiment, the second current flows through the second P-type transistor and is proportionate to the first current.
In one embodiment of the present invention, the current mirror includes a first N-type transistor with a drain coupled to ground, and a source and a gate coupled to a second end of the voltage-controlled variable resistor, so that the first current flows through the first N-type transistor. The current mirror also includes a second N-type transistor with a drain coupled to ground, a gate coupled to the second end of the voltage-controlled variable resistor, and a source coupled to a second terminal of the control voltage and then to V
DD
through a second resistor. In this embodiment, a third current flows through the second N-type transistor and is proportionate to the first current.
In one embodiment of the present invention, amplifying the control voltage to produce the validity signal involves using a differential receiver with a first input coupled to the first terminal of the control voltage and a second input coupled to the second terminal of the control voltage. The validity signal is the output of the differential receiver.
In one embodiment of the present invention, the first resistor and the second resistor are sized so that validity signal is asserted when both the first clock signal and the second clock signal are valid.
In one embodiment of the present invention, the first resistor and the second resistor are sized so that validity signal is asserted when at least one of the first clock signal and the second clock signal is valid.
In one embodiment of the present invention, the voltage-controlled variable resistor is implemented using at least one P-type transistor, wherein a gate input of the P-type transistor functions as the control-input of the voltage-controlled variable resistor.
In one embodiment of the present invention, the system additionally uses the validity signal to disable a data receiving circuit associated with the clock signal if the clock signal is not valid.
One embodiment of the present invention provides a system for detecting a valid clock signal at a clock receiver. This system operates by receiving a clock signal at the clock receiver, and directing the clock signal into a control input of a voltage-controlled variable resistor. Note that this voltage-controlled variable resistor is configured to remain in a high impedance state if the clock signal is floating. Next, the system uses the voltage-controlled variable resistor to control a first current, which is used to produce a control voltage. This control voltage is amplified to produce a validity signal indicating whether the clock signal is valid. The system additionally uses at least one capacitor to filter out fluctuations in the validity signal at the frequency of the clock signal.
REFERENCES:
patent: 4465379 (1984-08-01), Misawa et al.
patent: 6198310 (2001-03-01), Lohmueller
patent: 6593801 (2003-07-01), Hattori
Chakrabarti Prabhansu
Jong Jyh-Ming
Wu Chung-Hsiao
Yuan Leo
Lam Tuan T.
Park Vaughan & Fleming LLP
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