Method and apparatus for detecting the voltage on the VCC pin

Static information storage and retrieval – Floating gate – Particular biasing

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36518521, 36518533, 365226, 365229, G11C 1134, G11C 700

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active

058222464

ABSTRACT:
A method and apparatus for detecting the power supply voltage level of a circuit. A control circuit is used to enable or disable a first voltage level detector circuit and a second voltage level detector circuit. The first voltage level detector circuit consumes less power than the second voltage level detector circuit. The first voltage level detector circuit is enabled during all user modes of operation. The second voltage level detector circuit is enabled during the normal or active mode of operation and during power-up in all user modes of operation. The second voltage level detector circuit may also be enabled during a reduced power mode of operation that does not consume the least amount of power. A select circuit selects the output from either the first voltage level detector or the second voltage level detector. The first voltage level detector circuit is selected during the user mode that consumes the least amount of power. The second voltage level detector circuit is selected during the active or normal mode of operation and during power-up in all user modes of operation. The second voltage level detector circuit may also be selected during a reduced power mode of operation that does not consume the least amount of power.

REFERENCES:
patent: 5371705 (1994-12-01), Nakayama et al.
patent: 5444664 (1995-08-01), Kuroda et al.
patent: 5495453 (1996-02-01), Wociechowski et al.
patent: 5559717 (1996-09-01), Tedrow et al.
patent: 5610869 (1997-03-01), Yoo et al.
patent: 5627493 (1997-05-01), Takeuchi et al.
U.S. Patent Application of Tedrow, et al., entitled "High Precision Voltage Detector Utilizing Flash EEPROM Memory Cells", Application No.: 08/217,165, filed Mar. 23, 1994.

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