Method and apparatus for detecting single or multiple bit errors

Details Method and apparatus for detecting single or multiple bit errors Method and apparatus for detecting single or multiple bit errors

1993-05-20

1996-08-27

Gordon, Paul P.

Excavating

371 53, G06F 1110

Patent

active

055508499

ABSTRACT:
A method and system for detecting and correcting all single bit errors in a data word, for detecting all 2-bit errors regardless of whether the two bits in error are consecutive, and for detecting all consecutive 3-bit and 4-bit errors regardless of whether the three bits or four bits are in a single byte. In a preferred embodiment, a set of check bits are established for the data word by exclusively ORing a set of data bits that are unique to each check bit, storing the data bits and check bits, retrieving the data bits, generating a new set of check bits from the retrieved data bits, and comparing the new set of check bits against the old set to establish a syndrome pattern which may be expressed as a hexadecimal for comparison with hexadecimals previously assigned to the data bits.

REFERENCES:
patent: 4317201 (1982-02-01), Sedalis
patent: 4958350 (1990-09-01), Worley, III et al.
patent: 4979174 (1990-12-01), Cheng et al.
patent: 4993028 (1991-02-01), Hillis
patent: 5031181 (1991-07-01), Sako et al.

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