Pulse or digital communications – Repeaters – Testing
Patent
1988-10-14
1990-07-31
Safourek, Benedict V.
Pulse or digital communications
Repeaters
Testing
375118, 370102, H04L 2520, H04L 700
Patent
active
049455486
ABSTRACT:
A parallel asynchronous elasticity buffer. Selection of the address of a storage element for writing or reading of data is provided by asynchronous input and output pointers implemented using circular gray code counters. The buffer is initialized once during transmission of each frame of data so that the pointers do not select the same storage element for writing and reading at the same time. Write overflow or read underrun of a storage element is detected before any data corruption can occur by comparing the input and output pointers. An error condition is detected if the input and output pointers overlap for a threshold period, which can be shorter than the period required for writing or reading of a multibit data unit to or from the buffer. The overlap time period is determined by comparing the pointers at one or more sampling times corresponding to selected phases of a clock signal.
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Computer & Business Equipment Manufacturers Association, FDDI Physical Layer Protocol (PHY), Draft Proposed American National Standard, rev. 15, Sep. 1, 1987.
Iannarone John R.
Thompson Bruce W.
Digital Equipment Corporation
Huseman Marianne
Safourek Benedict V.
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