Method and apparatus for detecting errors in a data set

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371 39, 371 40, G06F 1112

Patent

active

042766460

ABSTRACT:
A method and apparatus are disclosed for detecting errors in a data set of sequential binary digits by initially separating alternating ones of the digits into data subsets and generating a cyclic redundancy code (CRC) for each data subset. After appending the CRC to the respective data subset to form corresponding code subsets, the code subsets are merged into a code set. To check for errors following any operation on the code set likely to introduce such errors, the code set is separated into the code subsets, each including the respective data subset CRC, and a CRC is generated on each code subset. Depending upon the form of the CRC generator, the code subset CRC value will indicate the presence of an error and, preferably, the location of such error. In the latter form, error correction can be conveniently performed as the data set is being reformed.

REFERENCES:
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patent: 3601798 (1971-08-01), Hsiao
patent: 3775746 (1973-11-01), Boudreau et al.
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patent: 4211996 (1980-07-01), Nakamura
"Megabit Bubble-Memory Chip Gets Support from LSI Family", Electronics, Apr. 26, 1979, pp. 105-111.
"CRC Error-Detection Schemes Ensure Data Accuracy", Electronic Data News, Sep. 5, 1978, pp. 119-123.
"Understanding Cyclic Redundancy Codes", Computer Design, Nov. 1975, pp. 93-99.

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