Method and apparatus for detecting clock loss

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S146000, C327S155000, C327S158000, C375S375000

Reexamination Certificate

active

07944261

ABSTRACT:
Method and apparatus for detecting clock loss in clock circuit. An example of the invention relates to detecting loss of a feedback clock signal input to a digital clock manager, where the feedback clock signal is derived from the reference clock signal. A clock divider is provided to produce a divided feedback clock signal from the feedback clock signal. A first pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of the reference clock signal. A second pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of an inversion of the reference clock signal. Detection logic is configured to detect whether each of the first pair of flip-flops and each of the second pair of flip-flops store the same value.

REFERENCES:
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patent: 6587534 (2003-07-01), Hassoun et al.
patent: 2003/0172327 (2003-09-01), Chen et al.
patent: 2005/0162199 (2005-07-01), Green et al.
patent: 2006/0280276 (2006-12-01), Chen et al.
XAPP462, “Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs,” Jan. 5, 2006, 1-68 pgs. Xilinx, Inc. 2100 Logic Drive, San Jose, CA.

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