Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-03-02
2003-01-07
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S425000
Reexamination Certificate
active
06505220
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing apparatus and method and a provision medium and, more particularly, to a signal processing apparatus and method and a provision medium arranged to enable detection of a unique pattern with high accuracy.
Regular digital multichannel broadcasting using a communication satellite (hereinafter referred to as “CS”) has been started in Japan and related various services have also been started or are about to be started. With respect to broadcasts using broadcasting satellites (hereinafter referred to as “BS”), a plan for a digital broadcasting service using the BS4 scheduled to be put into the sky has been reported in the Radio Regulatory Council.
Because BSs have power larger than that of CSs, use of a modulation system having a transmission efficiency higher than that of the quadrature phase shift keying (QPSK) system conventionally used with CSs is being studied. To ensure compatibility with other media such as CSs, ground waves and cable networks, transmission of a bit stream based on the socalled transport stream (hereinafter referred to as “TS”) prescribed in MPEG (Moving Picture Experts Group) 2 has been proposed. The TS is formed of 188-byte packets containing one-byte units of sync bytes. Since a Reed-Solomon code (hereinafter referred to as “RS code”) formed by adding 16-byte parity for error correction to the TS is being used in cable digital broadcasting and so on, use of the (204, 188) RS code formed on the TS has also been proposed for BS digital broadcasting.
With this background, in documents already made public: “Eisei ISDB niokeru saidaidensoyoryo to eiseihosopuran eno tekiyo (Maximum transmission capacity in satellite ISDB and application to satellite broadcasting plan)”, the Journal of Denshijohotsushin Gakkai (the Institute of Electronics, Information and Communication Engineers), Vol.J79-B-II No.7, “Eisei ISDB densohoshiki no kento (Study of satellite ISDB transmission system)”, a technical report from Eizojohomedia Gakkai (the Institute of Image Information and Television), Vol.21 BCS-97-12, etc., methods are proposed in which a convolutionally coded BPSK (binary phase shift keying) signal, a QPSK (quadrature phase shift keying) signal, or a trellis-coded 8PSK (octaphase shift keying) signal is used as the main signal portion for payload information other than the sync portion in the (204, 188) RS-coded TS, and in which transmission information such as information about the modulation method, the code rate, etc., (hereinafter referred to as “transmission multiplexing configuration control (TMSS) information”) is transmitted in a BPSK signal by using the sync portion of the TS.
FIG. 7
shows the configuration of an example of a satellite digital broadcast receiver with which one of the methods described in the above-mentioned documents is used. A broadcast signal from a BS, e.g., a BPSK-modulated signal is captured by an antenna
1
and frequency-converted into an intermediate frequency signal by an unillustrated frequency conversion circuit incorporated in the antenna
1
, and this intermediate frequency signal is supplied to a tuner
2
. After controlling the antenna
1
to receive the broadcast signal from the BS, the tuner
2
reads a signal of a program designated by a predetermined operation, and outputs the read signal to a second intermediate frequency circuit
3
. The second intermediate frequency circuit
3
shapes the spectrum of the signal input from the tuner
2
and performs predetermined amplification of the signal, and outputs the signal to multipliers
5
-
1
and
5
-
2
of an orthogonal demodulation circuit
4
.
Each of the multipliers
5
-
1
and
5
-
2
of the orthogonal demodulation circuit
4
multiplies together the BPSK-modulated signal input from the second intermediate frequency circuit
3
and one of two carriers input from a carrier reproduction circuit
11
in phase-orthogonal to each other, and outputs a multiplication result to the carrier reproduction circuit
11
, to a unique word detection circuit
120
, to a TMCC decoder
12
and to an error correcting circuit
13
via low-pass filters (LPF)
6
-
1
and
6
-
2
.
The unique word detection circuit
120
detects from the input signal a unique pattern formed as a frame sync signal, and outputs a detection result to the TMCC decoder
12
. The TMCC decoder
12
decodes a TMCC signal in the input signal and outputs a decoding result to the carrier reproduction circuit
11
and to the error correcting circuit
13
.
The carrier reproduction circuit
11
is supplied with a signal representing a phase error of the carriers which occurs when the TMCC decoder decodes the TMCC signal. The carrier reproduction circuit
11
reproduces two orthogonal carriers according to the supplied signal and outputs the reproduced carriers to the orthogonal demodulation circuit
4
. The error correcting circuit
13
has unillustrated components: a Viterbi decoder, a Reed-Solomon decoder and an interleave circuit. The error correcting circuit
13
corrects a transmission channel error in the input main signal (QPSK signal) based on the TMCC signal from the TMCC decoder
12
, and outputs the corrected signal.
FIG. 8
shows the configuration of an example of the unique word detection circuit
120
. The unique word detection circuit
120
is formed by a differential demodulation circuit
121
and a unique word differential pattern detection circuit
122
. A register
123
-
1
of the differential demodulation circuit
121
delays, for example, the sync signal of the BPSK signal input from the orthogonal demodulation circuit
4
by a predetermined time period (corresponding to one symbol), and outputs the delayed signal to a multiplier
124
-
1
. The multiplier
124
-
1
multiplies together the signal (sync signal) directly input from the orthogonal demodulation circuit
4
and the signal delayed by the predetermined time period and supplied from the register
123
-
1
, and outputs a multiplication result to an adder
125
.
The register
123
-
2
of the differential demodulation circuit
121
also delays, for example, the orthogonal signal of the BPSK signal input from the orthogonal demodulation circuit
4
by the predetermined time period (corresponding to one symbol), and outputs the delayed signal to a multiplier
124
-
2
. The multiplier
124
-
2
multiplies together the signal (orthogonal signal) directly input from the orthogonal demodulation circuit
4
. and the signal delayed by the predetermined time period and supplied from the register
123
-
2
, and outputs a multiplication result to the adder
125
.
The adder
125
adds together the signal input from the multiplier
124
-
1
and the signal input from the multiplier
124
-
2
, and supplies an addition result to a binalization circuit
126
of the unique word differential pattern detection circuit
122
.
The binalization circuit
126
of the unique word differential pattern detection circuit
122
binalizes the signal input from the adder
125
of the differential demodulation circuit
121
by a data width of one bit, and outputs the binalized signal to a register
127
-
1
. The register
127
-
1
stores the signal from the binalization circuit
126
and outputs the stored signal to a register
127
-
2
and to an exclusive-OR circuit (hereinafter referred to as “EX-OR”)
128
-
1
in the next stage in synchronization with a clock. The EX-OR
128
-
1
performs exclusive-OR processing of the signal from the register
127
-
1
and a predetermined signal S
1
separately input, and outputs a processing result to a NOR circuit
130
.
Similarly, each of registers
127
-
2
to
127
-(n−1) records the input signal and outputs the recorded signal to one of the registers
127
-
3
to
127
-(n−1) and to one of EX-ORs
128
-
1
to
128
-(n−1) in the next stage in synchronization with the clock. The register
127
-(n−1) outputs the stored signal to the EX-OR
128
-(n−1). Each of the EX-ORs
128
-
1
to
128
-(n−1) performs exclusive-OR processing of
Lerner David Littenberg Krumholz & Mentlik LLP
Malzahn David H.
Sony Corporation
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